English
Language : 

AD8319_07 Datasheet, PDF (13/20 Pages) Analog Devices – 1 MHz to 10 GHz, 40 dB Log Detector/Controller
AD8319
For example, PINTERCEPT for a sinusoidal input signal expressed in
terms of dBm (decibels referred to 1 mW), in a 50 Ω system is
PINTERCEPT(dBm) =
PINTERCEPT(dBV) − 10 × log10(Z0 × 1 mW/1 Vrms2) =
2 dBV − 10 × log10(50×10-3) = 15 dBm
(7)
For a square wave input signal in a 200 Ω system
PINTERCEPT = −1 dBV − 10 × log10[(200 Ω × 1 mW/1Vrms2)] =
6 dBm
Further information on the intercept variation dependence upon
waveform can be found in the AD8313 and AD8307 data sheets.
SETTING THE OUTPUT SLOPE IN
MEASUREMENT MODE
To operate in measurement mode, VOUT must be connected to
VSET. Connecting VOUT directly to VSET yields the nominal
logarithmic slope of −22 mV/dB. The output swing corresponding
to the specified input range is then 0.35 V to 1.5 V. The slope
and output swing can be increased by placing a resistor divider
between VOUT and VSET (that is, one resistor from VOUT to
VSET and one resistor from VSET to ground). The input imped-
ance of VSET is 40 kΩ. Slope-setting resistors should be kept below
20 kΩ to prevent this input impedance from affecting the
resulting slope. If two equal resistors are used (for example,
10 kΩ/10 kΩ), the slope doubles to −44 mV/dB.
AD8319
VOUT
VSET
–44mV/dB
10kΩ
10kΩ
Figure 28. Increasing the Slope
CONTROLLER MODE
The AD8319 provides a controller mode feature at Pin VOUT.
Using VSET for the setpoint voltage, it is possible for the AD8319
to control subsystems, such as power amplifiers (PAs), variable
gain amplifiers (VGAs), or variable voltage attenuators (VVAs)
that have output power that increases monotonically with
respect to their gain control signal.
To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET
input; VOUT is connected to the gain control terminal of the
VGA and the detector’s RF input is connected to the output of
the VGA (usually using a directional coupler and some
additional attenuation). Based on the defined relationship
between VOUT and the RF input signal when the device is in
measurement mode, the AD8319 adjusts the voltage on VOUT
(VOUT is now an error amplifier output) until the level at the
RF input corresponds to the applied VSET. When the AD8319
operates in controller mode, there is no defined relationship
between the VSET and VOUT voltages; VOUT settles to a value that
results in the correct input signal level appearing at INHI/INLO.
For this output power control loop to be stable, a ground-
referenced capacitor must be connected to the CLPF pin. This
capacitor, CFLT, integrates the error signal (in the form of a
current) to set the loop bandwidth and ensure loop stability.
Further details on control loop dynamics can be found in the
AD8315 data sheet.
VGA/VVA
RFIN
DIRECTIONAL
COUPLER
ATTENUATOR
GAIN
CONTROL
VOLTAGE
47nF
VOUT
INHI
52.3Ω
AD8319
INLO VSET
DAC
47nF
CLPF
CFLT
Figure 29. AD8319 Controller Mode
Decreasing VSET, which corresponds to demanding a higher
signal from the VGA, increases VOUT. The gain control voltage
of the VGA must have a positive sense. A positive control
voltage to the VGA increases the gain of the device.
The basic connections for operating the AD8319 in an automatic
gain control (AGC) loop with the ADL5330 are shown in
Figure 30. The ADL5330 is a 10 MHz to 3 GHz variable gain
amplifier. It offers a large gain control range of 60 dB with
±0.5 dB gain stability. This configuration is similar to Figure 29.
The gain of the ADL5330 is controlled by the output pin of the
AD8319. This voltage, VOUT, has a range of 0 V to near VPOS.
To avoid overdrive recovery issues, the AD8319 output voltage
can be scaled down using a resistive divider to interface with the
0 V to 1.4 V gain control range of the ADL5330.
A coupler/attenuation of 21 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8319 (approximately −5 dBm
at 900 MHz).
+5V
+5V
RF INPUT
SIGNAL
100pF
100pF
VPOS COMM
INHI
OPHI
ADL5330
INLO
OPLO
GAIN
120nH
120nH
100pF
100pF
RF OUTPUT
SIGNAL
DIRECTIONAL
COUPLER
4.12kΩ
+5V
10kΩ
DAC
SETPOINT
VOLTAGE
1nF
VOUT
VSET
VPOS
INHI
AD8319
LOG AMP
CLPF
TADJ
INLO
COMM
47nF
52.3Ω
47nF
18kΩ
ATTENUATOR
Figure 30. AD8319 Operating in Controller Mode to Provide Automatic Gain
Control Functionality in Combination with the ADL5330
Rev. A | Page 13 of 20