AD8311_15 Datasheet, PDF (13/24 Pages) Analog Devices – 50 dB GSM PA Controller

AD8311
First, the summed detector currents are written as a function of
the input power.
I_DET = I_SLP × P_IN + I _INT
(3)
where:
IDET is the partially filtered demodulated signal, whose steady-
state average value is extracted through the subsequent
integration step.
ISLP is the slope, which has a value of 5.75 μA/dB.
PIN is the input power in dBm (assuming 50 Ω input match).
IINT is the current intercept which, as previously noted, is
dependent on the RF waveform (not the envelope). Assuming
a sinusoidal input, IINT is 350 μA.
The current generated by the setpoint interface is simply
I _SET = V_SET R_SET
(4)
where the RSET resistor is 4.1 kΩ. The difference between this
current and IDET is applied to the loop filter capacitor CFLT. At
this point note that the inclusion of a filter resistor, RFLT, can be
helpful in improving the phase margin at low powers where the
PA control gain (that is, ∂POUT/∂VAPC) is large, as is described
later in this section. For now assume that RFLT is zero. It follows
that the voltage appearing on this capacitor, VFLT, is the time-
integral of the difference current.
( ) ( ) V_FLT s = I _SET − I _DET sC_FLT
(5)
= ^{VSET RSET − I SLP × PIN − I INT}
(6)
sC_FLT
The control output VAPC is slightly greater than this, since the gain
of the output buffer is ×1.35, plus a slight offset voltage. The
polarity is such that VAPC rises to its maximum value for any value
of VSET greater than the equivalent value of PIN. That is, the
AD8311 seeks to drive the RF power to its maximum value
whenever it falls below the setpoint. The use of exact integration
results in a dc error that is theoretically zero, and the logarithmic
detection law would ideally result in a constant response time
following a step change of either the setpoint or the power level if
the power-amplifier control function were likewise linear-in-dB.
This latter condition is rarely true, however, and it follows that in
practice the loop response time depends on the power level. This
effect can strongly influence the design of the control loop.
Equation 6 can be restated as
V_APC (s) = ^VSET
− V_SLP ×
sT
P_IN
− V_INT
(7)
where:
VSLP is ISLP × RSET, which has a value of 24 mV/dB.
VINT is the voltage intercept given by IINT × RSET, which has a
value of 1.44 V.
T is the effective time constant for the integration and is equal
to RSET × CFLT/1.35. The factor of 1.35 arises because of the
voltage gain of the buffer.
So the open-loop integration time constant can be written as
T_OpenLoop = R_SET × C_FLT 1.35
(8)
To assess the closed-loop performance, refer to the block
diagram in Figure 28 and calculate the loop transfer function.
In general, the buffer time constant (τBUFFER) and the log amp
time constant (τLOGAMP) can be neglected, except in the case of
very high PA control function gains (> than 500 dB/V) and/or
very wide PA control port bandwidths. Assuming that the
frequency response of the output buffer and the log amp can be
neglected, the overall transfer function can be expressed as
POUT =
[ ] ( ) ( ) I _SET +I _SLP × 30 − I _INT × 1.35 × G_PA 1 + sτ_PA ×(1 sC_FLT ) ₍₉₎
[ ( )] ( ) 1 + I _SLP × 1.35× G_PA 1 + sτ_PA sC _FLT
Here, GPA is the PA control function gain ∂POUT/∂VAPC given in
dB/V, and the factor of −30 is due to the coupler.
The input power to the log amp, PIN, is given in dBm and
therefore is simply POUT of the PA minus the coupler value,
typically −30 dB, or PIN = POUT − 30.
Equation 9 assumes that the next parasitic pole in the control
loop comes from the PA. For a typical PA, a 1 MHz pole is not
unusual, making this a good assumption. Therefore, except for
in the case of a very wide bandwidth on the PA control port
(>10 MHz), the response time and stability of the control loop is
mainly determined by the characteristics of the PA. This is true
for both the gain and the phase response. It is essential to
understand both the magnitude and frequency response of the
power amplifier control port.
I_SET
+
I_ERR
_
I_DET
1
sC_FLT ^{+ RFLT}
V_FLT
1.35
V_APC
1 + sτ_BUFFER
G_PA (dB/V)
1 + sτ_PA
P_OUT
I_SLP P_IN + I_INT
P_IN
–30dB
1 + sτ_LOGAMP
COUPLER
Figure 28. Control Loop Block Diagram
Rev. A | Page 13 of 24