English
Language : 

AD7771 Datasheet, PDF (13/14 Pages) Analog Devices – 8-Ch, 24-Bit Simultaneous Sampling ADC
AD7771
Preliminary Technical Data
Pin No. Mnemonic
26
DOUT2
27
DOUT1
28
DOUT0
29
DCLK
30
DRDY
31
XTAL1
32
XTAL2/MCLK
33
START
34
SYNC_OUT
35
SYNC_IN
36
RESET
37
AIN7+
38
AIN7−
39
AIN6+
40
AIN6−
41
REF2+
42
REF2−
43
AVDD1B
44
AVSS1B
45
AIN5+
46
AIN5−
47
AIN4+
48
AIN4−
49
REF_OUT
50
AVSS2B
51
AReg2Cap
52
AVDD2B
53
AVSS3
54
FORMAT1
55
FORMAT0
56
CLK_SEL
57
VCM
58
AVDD2A
59
AReg1Cap
Type
Direction
Digital Output IO
Digital Output Output
Digital Output Output
Digital Output Output
Digital Output Output
Description
Data output pin 2. If the part is configured in daisy-chain mode, this pin acts
as an input pin.
Data output pin 1
Data output pin 0
Data Output Clock
Data Output Ready
Clock
Input
Clock
Input
Digital Input Input
Digital Output Input
Digital Input Input
XTAL1 input connection, If CMOS is used as a clock source, connect tie this
pin to DGND.
XTAL2 input connection or CMOS clock
Synchronization pulse. This pin is used to synchronize internally an
external START asynchronous pulse with MCLK. The synchronize signal is
shift out by SYNC_OUT pin.Tie to DGND is not used.
Synchronization signal. This pin generates a synchronous pulse
SYNC_IN reset the internal SINC filters.
Digital Input Input
Asynchronous Reset Pin. Resets all registers to default value. I
Analog Input
Analog Input
Analog Input
Analog Input
Reference
Input
Input
Input
Input
Input
Reference
Input
Supply
Supply
Supply
Supply
Analog Input Input
Analog Input Input
Analog Input Input
Analog Input Input
Reference
Output
Supply
Supply
Supply
Output
Supply
Supply
Supply
Supply
Digital Input Input
Digital Input Input
Digital Input Input
Analog Output Output
Supply
Input
Supply
Output
Analog Input Channel 7
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 6
Positive Reference Input 1 for Channels 4 to 7, recommended value REF2− +
2.5V
Negative Reference Input for Channels 4 to 7, typically AVSSx. Connect all
REFx− pins to the same potential
Positive Front End Analog Supply for Channels 4 to 7. This pin should be
connected together with AVDD1A
Negative Front End Analog Supply for Channels 4 to 7, typical
-1.65V(Dual Supply) or AGND (Single Supply).
Connect all AVSSx pins together
Analog Input Channel 5
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 4
2.5V Reference Output
Negative Analog supply. Connect all AVSSx pins together.
Analog LDO output. Decouple to AVSS2 with 1uF cap
Positive Analog supply, this pin should be connected together with AVDD2A
Negative Analog Ground. Connect all AVSSx pins together
Output data frame,
Output data frame,
Select Clock Source,
Common Mode Voltage Output, (AVDD1−AVSS)/2
Analog supply, from 2.2V to 3.6V. AVSS2x should not be lower than
ARegxCap. AVSS2x should not be lower than ARegxCap.Connected This pin
should be connected together with AVDD2B
Analog LDO output. Decouple to AVSS with 1uF cap.
Rev. PrC | Page 12 of 13