AD7721 Datasheet, PDF (13/16 Pages) Analog Devices – CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC

AD7721
MICROCOMPUTER/MICROPROCESSOR INTERFACING
The AD7721 has a variety of interfacing options. It offers two
operating modes—serial and parallel.
Serial Interfacing
In serial mode, the AD7721 can be directly interfaced to several
DSPs. In all cases, the AD7721 operates as the master with the
DSP acting as the slave. The AD7721 provides its own serial
clock to clock the digital word from the AD7721 to the DSP.
The serial clock is a buffered version of the master clock CLK.
The frame synchronization signal to the AD7721 and the DSP
is provided by the DRDY signal.
Because the serial clock from the AD7721 has the same frequency
as the master clock, DSPs that can accept high serial clock fre-
quencies are required. When the AD7721 is being operated
with a 15 MHz clock, Analog Devices’ ADSP-2106x SHARC^®
DSP is suitable as this DSP can accept very high serial clocks.
The 40 MHz version of this DSP can accept a serial clock of
40 MHz maximum. To interface the AD7721 to other DSPs,
the master clock frequency of the AD7721 can be reduced so
that it equals the maximum allowable frequency of the serial
clock for the DSP. This will cause the sampling rate, the output
word rate and the bandwidth of the AD7721 to be reduced by a
proportional amount. The ADSP-21xx family can operate with
a maximum serial clock of 13.824 MHz, the DSP56002 uses a
maximum serial clock of 13.3 MHz while the TMS320C5x-57
accepts a maximum serial clock of 10.989 MHz.
When the AD7721 is being operated with a low master clock
frequency (< 8 MHz), DSPs such as the TMS320C20/C25 and
DSP56000/1 can be used. Figures 13 to 15 show the interfaces
between the AD7721 and several DSPs. In all cases, CS, RD
and WR are permanently hardwired to DGND.
AD7721 to ADSP-21xx Interface
Several of the ADSP-21xx family can interface directly to the
AD7721. DRDY is used as the frame sync signal for both the
ADSP-21xx and the AD7721. DRDY, which goes high for two
clock cycles when a conversion is complete, can also be used as
an interrupt signal if required. Figure 13 shows the AD7721
interface to the ADSP-21xx. For the ADSP-21xx, the bits in
the serial port control register should be set up as RFSR = 1
(a frame sync is needed for each transfer), SLEN = 15 (16 bit
word lengths), RFSW = 0 (normal framing mode for receive
operations), INVRFS = 0 (active high RFS), IRFS = 0 (external
RFS), and ISCLK = 0 (external serial clock).
ADSP-21xx
IRQ
DR
RFS
SCLK
AD7721
DRDY
RFS
WR
RD
CS
SDATA
SCLK
Figure 13. AD7721 to ADSP-21xx Interface
The interface between the AD7721 and the ADSP-2106x
SHARC DSP is the same as shown in Figure 13, but the DSP is
configured as follows: SLEN = 15 (16-bit word transfers),
SENDN = 0 (the MSB of the 16-bit word will be received by
the DSP first), ICLK = 0 (an external serial clock will be used),
RFSR = 0 (a frame sync is required for every word transfer),
IRFS = 0 (the receive frame sync signal is external), CKRE = 0
(the receive data will be latched into the DSP on the falling
clock edge), LAFS = 0 (the DSP begins reading the 16 bit word
after the DSP has identified the frame sync signal rather than
the DSP reading the word at the same instant as the frame sync
signal has been identified), LRFS = 0 (RFS is active high).
AD7721 to DSP56002 Interface
Figure 14 shows the AD7721 to DSP56002 interface. If the
AD7721 is being used at a lower clock frequency (≤5.128 MHz),
the DSP56000 or DSP56001 can be used. The interface will be
similar for all three DSPs. To interface the DSP56002 to the
AD7721, the DSP56002 is configured as follows: SYN = 1
(synchronous mode), SCD1 = 0 (RFS will be an input),
GCK = 0 (a continuous clock will be used), SCKD = 0 (the
serial clock will be external), WL1 = 1, WL0 = 0 (transfers will
be 16 bits wide), FSL1 = 0, FSL0 = 1 (the frame sync will be
active at the beginning of each transfer).
DSP56002
IRQ
SRD
SC1
SCK
AD7721
DRDY
RFS
WR
RD
CS
SDATA
SCLK
Figure 14. AD7721 to DSP56002 Interface
Alternatively, the DSP56002 can be operated in asynchronous
mode (SYN = 0). In this mode, the serial clock for the Receive
section in inputted to the SC0 pin. This is accomplished by
setting bit SCD0 to 0 (external Rx clock).
AD7721 to TMS320C20/C25/C5x Interface
Figure 15 shows the AD7721 to TMS320C20/C25/C5x inter-
face. For the TMS320C5x, FSR and CLKR are automatically
configured as inputs. The serial port is configured as follows:
FO = 0 (16-bit word transfers), FSM = 1 (a frame sync occurs
for each transfer). Figure 15 shows the interface diagram when
the AD7721 is being interfaced to the TMS320C20 and the
TMS320C25 also but, these DSPs can be used only when the
AD7721 is being used at a lower frequency such as 5 MHz
(C25) or 2.56 MHz (C20).
INT0
TMS320C
20/25/5x
DR
FSR
CLKR
AD7721
DRDY
RFS
WR
RD
CS
SDATA
SCLK
Figure 15. AD7721 to TMS320C20/25/5x Interface
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
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