AD1837A_15 Datasheet, PDF (13/24 Pages) Analog Devices – 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec

AD1837A
Control Register 2, the serial mode can be changed to right-
justified (RJ), left-justified DSP (DSP), or left-justified (LJ).
In the RJ mode, it is necessary to set Bits 4 and 5 to define the
width of the data-word.
The DAC serial data input mode defaults to I²S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2. The
word width defaults to 24 bits but can be changed by reprogram-
ming Bits 3 and 4 in DAC Control Register 1.
Packed Modes
The AD1837A packed mode allows a DSP or other controller to
write to all DACs and read all ADCs using one input data pin
and one output data pin. Packed Mode 256 refers to the number
of BCLKs in each frame. The LRCLK is low while data from a
left channel DAC or ADC is on the data pin and high while data
from a right channel DAC or ADC is on the data pin. DAC data is
applied on the DSDATA1 pin, and ADC data is available on the
ASDATA pin. Figures 7 to 10 show the timing for the packed
mode. Packed mode is available for 48 kHz and 96 kHz.
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external stereo
ADCs to be interfaced to the AD1837A to provide 8-in/8-out
operation. In addition, this mode supports glueless interface to a
single SHARC^® DSP serial port, allowing a SHARC DSP to
access all eight channels of analog I/O. In this special mode,
many pins are redefined; see Table IV for a list of redefined pins.
The auxiliary and the TDM interfaces are independently
configurable to operate as masters or slaves. When the auxiliary
interface is set as a master, by programming the Auxiliary Mode
bit in ADC Control Register 2, AUXLRCLK and AUXBCLK are
generated by the AD1837A. When the auxiliary interface is set
as a slave, AUXLRCLK and AUXBCLK need to be generated
by an external ADC, as shown in Figure 13.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs gener-
ated by the AD1837A. In slave mode, FSTDM and BCLK are
inputs and should be generated by the SHARC. Both 48 kHz
and 96 kHz operations are available (based on a 12.288 MHz or
24.576 MHz MCLK) in this mode.
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
I²S MODE—16 BITS TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LSB
MSB
DSP MODE— 16 BITS TO 24 BITS PER CHANNEL
1/ f_S
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT f_S EXCEPT FOR DSP MODE, WHICH IS 2 Ï« f_S.
3. BCLK FREQUENCY IS NORMALLY 64 Ï« LRCLK BUT MAY BE OPERATED IN BURST MODE.
LSB
Figure 4. Stereo Serial Modes
REV. A
–13–