ADXL50_15 Datasheet, PDF (12/16 Pages) Analog Devices – Monolithic Accelerometer With Signal Conditioning

ADXL50
DEMODULATOR CAPACITOR, C1
The demodulator capacitor is connected across Pins 2 and 3 to
filter the demodulated signal from the sensor beam and to set
the bandwidth of the force balance control loop. This capacitor
may be used to approximately set the bandwidth of the acceler-
ometer. A capacitor is always required for proper operation.
For example, to reduce the average power to 5 mW from its
typical 50 mW, the power should be on 10% of the time. With
the power on for 1 ms and off for 9 ms, a maximum sample rate
of 100 Hz is achievable. Further reduction in average power can
be realized with lower sample rates.
The frequency response of the ADXL50 exhibits a single pole
POWER
+5V
roll-off response whose nominal 3 dB frequency is set by the
SUPPLY
(V)
following equation:
0V
f_{3 dB} = (28.60/C1 in µF) ± 40%
A nominal value of 0.022 µF is recommended for C1. In gen-
V_FINAL
eral, the design bandwidth should be set 40% higher than the
OBSOLETE minimum desired system bandwidth due to the ±40% tolerance.
A minimum value of 0.015 µF is required, (over temperature
and system life), to prevent device instability or oscillation. The
demodulation capacitor should be a low leakage, low drift ce-
ramic type with an NPO (best) or X7R (good) dielectric.
In general, it’s best to use the recommended 0.022 µF capacitor
across the demodulator pins and perform any additional low-
pass filtering using the buffer amplifier. Using a large denomina-
tor capacitor for low-pass filtering has the disadvantage that the
capacitive sensor will be slow to respond to rapid changes in
acceleration and, therefore, the full shock survivability of the
device could be compromised. The use of the buffer for low-
pass filtering generally results in smaller capacitance values and
better overall performance. It is also a convenient and more pre-
cise way to set the system bandwidth. Post filtering allows band-
width to be controlled accurately by component selection and
avoids the ± 40% demodulation tolerance. Note that signal noise
V_OUT
(V)
T₀
0.2
0.4
0.6
0.8
1.0
TIME – ms
Figure 21. Power-On Settling Time when Power Cycling
SYSTEM BANDWIDTH CONTROL AND POST
FILTERING
Unlike piezoresistive sensors, the resonant frequency of the
ADXL50’s capacitive sensor element is typically greater than
20 kHz and does not limit the useful bandwidth of the device.
Usually, the resonant frequency of the beam appears as a peak
in the bandwidth response at approximately 24 kHz with a Q of
is proportional to the square root of the bandwidth of the
3 to 4, as shown in Figure 22.
ADXL50 and may be a consideration in component selection—
see section on noise.
When using the recommended 0.022 µF demodulator capacitor,
be advised that the nominal 1300 Hz pole it establishes within
Care should be taken to reduce or eliminate any leakage paths
the device can vary ± 40%. Therefore, if additional low-pass
from the demodulator capacitor pins to common or to the +5 V ^{filtering is used—at frequencies much above 600 Hz—the two}
pin. Even a small imbalance in the leakage paths from these pins poles may interact and result in a net circuit bandwidth that is
will result in offset shifts in the zero-g bias level. As an example, lower than expected.
an unbalanced parasitic resistance of 30 MΩ from either
demodulator pin to ground will result in an offset shift at V_PR of
190
approximately 50 mV. Conformal coating of PC boards with a
AMPLITUDE
high impedance material is recommended to avoid leakage prob-
19
lems due to aging or moisture.
1.9
REDUCING THE AVERAGE POWER CONSUMPTION OF
THE ADXL50
The ADXL50 is a versatile accelerometer that can be used in a
0.19
0.022µ F
0.015µ F
0.010µ F
0.005µ F
0
wide variety of applications. In some battery powered applica-
tions, such as shipping recorders, power consumption is a criti-
–90
cal parameter. The ADXL50 typically draws 10 mA current
PHASE
from a 5 V power supply which may exceed the power budgeted
–180
for the accelerometer.
For such applications, the ADXL50 can be successfully power
cycled, where the power is turned on only during the period
when data is sampled. Figure 21 illustrates the power-on settling
of the ADXL50 during cycling where the output amplifier has
a gain of one with no filtering. The settling time-constant is
approximately 0.12 ms, waiting l ms before sampling ensures
maximally accurate readings.
100
1k
10k
FREQUENCY – Hz
Figure 22. Frequency Response of the ADXL50 for Various
Demodulator Capacitors
–12–
REV. B