ADV7180 Datasheet, PDF (12/112 Pages) Analog Devices – 10-Bit, 4 x Oversampling SDTV Video Decoder

ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
40-LEAD LFCSP
DVDDIO 1
SFL 2
DGND 3
DVDDIO 4
P7 5
P6 6
P5 7
P4 8
P3 9
P2 10
PIN 1
INDICATOR
ADV7180
LFCSP
TOP VIEW
(Not to Scale)
30 A_IN3
29 A_IN2
28 AGND
27 AVDD
26 VREFN
25 VREFP
24 AGND
23 A_IN1
22 TEST_0
21 AGND
Figure 7. 40-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40
Pin No.
Mnemonic
Type Function
3, 15, 35, 40 DGND
G
Ground for Digital Supply.
21, 24, 28
AGND
G
Ground for Analog Supply.
1, 4
DVDDIO
P
Digital I/O Supply Voltage (3.3 V).
14, 36
DVDD
P
Digital Supply Voltage (1.8 V).
27
AVDD
P
Analog Supply Voltage (1.8 V).
20
PVDD
P
PLL Supply Voltage (1.8 V).
23, 29, 30
AIN1 to AIN3
I
Analog Video Input Channels.
5 to 10, 16, 17 P7 to P2, P1, P0 O
Video Pixel Output Port.
39
HS
O
Horizontal Synchronization Output Signal.
38
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
37
VS/FIELD
O
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
33
SDATA
I/O I²C Port Serial Data Input/Output Pin.
34
SCLK
I
I²C Port Serial Clock Input. Maximum clock rate of 400 kHz.
32
ALSB
I
Selects the I²C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a
write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC.
31
RESET
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
11
LLC
O
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or
down according to video line length.
13
XTAL
I
Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
12
XTAL1
O
This pin should be connected to the 28.6363 MHz crystal, or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
18
PWRDWN
I
A logic low on this pin places the ADV7180 into power-down mode.
19
ELPF
I
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 53.
2
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video
encoder.
26
VREFN
O
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
25
VREFP
O
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
22
TEST_0
I
This pin must be tied to DGND.
Rev. A | Page 12 of 112