ADUC7128_15 Datasheet, PDF (12/92 Pages) Analog Devices – Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC

ADuC7128/ADuC7129
Table 6. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
Description
tSL
SCLOCK low pulse width¹
tSH
SCLOCK high pulse width¹
tDAV
Data output valid after SCLOCK edge
tDOSU
Data output setup before SCLOCK edge
tDSU
Data input setup time before SCLOCK edge²
tDHD
Data input hold time after SCLOCK edge²
tDF
Data output fall time
tDR
Data output rise time
tSR
SCLOCK rise time
tSF
SCLOCK fall time
Min
1 × tUCLK
2 × tUCLK
1 _{tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2}CD_.
2 _{tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.}
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
5
5
5
5
Max
2 × tHCLK + 2 × tUCLK
75
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI
MISO
t_SH
t_SL
t_DOSU
t_DAV
t_DF
MSB
t_DR
BIT 6 TO BIT 1
t_SR
t_SF
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
t_DSU
t_DHD
Figure 7. SPI Master Mode Timing (PHASE Mode = 0)
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