ADF4360-9 Datasheet, PDF (12/24 Pages) Analog Devices – Clock Generator PLL with Integrated VCO

ADF4360-9
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 19. To
allow the user to optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable via Bit PL1 and Bit PL2 in the control latch.
Four current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −9 dBm, −6 dBm,
−3 dBm, and 0 dBm, respectively, using the correct shunt inductor
to VDD and ac coupling into a 50 Ω load. Alternatively, both
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
Another feature of the ADF4360 family is that the supply
current to the RF output stage is shut down until the part
achieves lock, as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.
RF_OUTA
RF_OUTB
VCO
BUFFER
Figure 19. RF Output Stage
DIVOUT STAGE
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of DIVOUT
is controlled by D3, D2, and D1 in the control latch. The full
truth table is shown in Figure 23. Figure 20 shows the DIVOUT
section in block diagram form.
A COUNTER/2 OUTPUT
A COUNTER OUTPUT
R COUNTER OUTPUT
N COUNTER OUTPUT
MUX
Data Sheet
DV_DD
CONTROL
DIVOUT
Figure 20. DIVOUT Circuit
DGND
The primary use of this pin is to derive the lower frequencies
from the VCO by programming various divider values to the
auxiliary A divider. Values ranging from 2 to 31 are possible.
The duty cycle of this output is 1/A times 100%, with the logic
high pulse width equal to the inverse of the VCO frequency.
That is,
Pulse Width [seconds] = 1/fVCO (Frequency [Hz])
See Figure 21 for a graphical description. By selecting the
divide-by-2 function, this divided down frequency can in turn
be divided by 2 again. This provides a 50% duty cycle in contrast to
the A counter output, which may be more suitable for some
applications (see Figure 21).
f_VCO
f_VCO/A (A = 4)
f_VCO/2A (A = 4)
Figure 21. DIVOUT Waveforms
Rev. B | Page 12 of 24