ADC912A Datasheet, PDF (12/16 Pages) Analog Devices – CMOS Microprocessor-Compatible 12-Bit A/D Converter

ADC912A
CIRCUIT LAYOUT GUIDELINES
As with any high-speed A/D converters, good circuit layout
practice is essential. Wire-wrap boards are not recommended
due to stray pickup of the high-frequency digital noise. A PC
board offers the best results. Digital and analog grounds
should be separated even if they are ground planes instead of
ground traces. Do not lay digital traces adjacent to high-
impedance analog traces. Avoid digital layouts that radiate
high-frequency clock signals; i.e., do not lay out digital signal
lines and ground returns in the shape of a loop antenna. Shield
the analog input if it comes from a different PC board source.
Set up a single point ground at AGND (Pin 3) of the ADC912A;
tie all other analog grounds to this point. Also tie the logic
power supply ground, but no other digital grounds, to this point
(see Figure 21). Low impedance analog and digital power sup-
ply common returns are essential to low noise operation of the
ADC. Their trace widths should be as wide as possible. Good
power supply bypass capacitors located near the ADC package
ensure quiet operation. Place a 10 µF capacitor in parallel with a
0.01 µF ceramic capacitor across V_DD to ground and V_SS to
ground (near Pin 3).
+15V
ANALOG
SUPPLY
GND
–15V
COMMON
GROUND
DIGITAL
SUPPLY
+5V
RETURN
ANALOG
CIRCUITS
AGND
V_SS DGND V_DD
ADC912A
DIGITAL
CIRCUITS
Figure 21. Power Supply Grounding
In applications where the ADC912A data outputs and control
signals are connected to a continuously active microprocessor
bus, it is possible to get LSB level errors in conversion results.
These errors are due to a feedthrough from the microprocessor
to the internal comparator. The problem can be minimized by
forcing the microprocessor into a WAIT state during conversion
(see Slow-Memory microprocessor interfacing). An alternate
method is isolation of the data bus with three-state buffers, such
as the 74HC541.
INTERFACING TO THE TMS32010 DSP PROCESSOR
Figure 22 shows an ADC912A to TMS32010 interface. The
ADC912A is operating in the ROM mode. The interface
is designed for the maximum TMS32010 clock frequency
of 20 MHz.
ADDRESS BUS
PA₀ PA₂
CS
ADDRESS _EN
DEN
DECODE
RD
ADC912A*
D₁₁
D_0/8
HBEN
DATA BUS
TMS32010*
D₁₅
D₀
*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY
Figure 22. ADC912A to TMS32010 DSP Processor Interface
The ADC912A is mapped at a user-selected port address (PA).
The following I/O instruction starts a conversion and reads the
previous conversion into the data memory:
IN DATA, PA
PA = Port Address
DATA = Data Memory Location
When conversion is complete, a second I/O instruction reads the
new data into the data memory and starts another conversion.
Sufficient A/D conversion time must be allowed between I/O
instructions. The very first data read after system power-up
should be discarded.
USING WAIT STATES
The TMS32020 DSP processor has the added capability of
WAIT states. This feature simplifies the hardware required for
slow memory devices by extending the microprocessor bus
access time. Figure 23 shows an ADC912A to TMS32020
interface using one WAIT state to guarantee data interface at
the full 20 MHz clock frequency. This WAIT state extends the
bus access time by 200 ns. In this circuit the ADC912A operated
in the ROM mode where each input instruction (IN DATA, PA)
takes the previous conversion result and stores it in memory. The
next input instruction must be delayed for the length of the A/D
conversion time so that a new conversion result can be read.
–12–
REV. B