AD974BRSZ Datasheet, PDF (12/20 Pages) Analog Devices – 4-Channel, 16-Bit, 200 kSPS Data Acquisition System

AD974
EXTERNAL CONTINUOUS CLOCK DATA READ DURING
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 9 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a continu-
ous external clock with the generation of a SYNC output. What
permits the generation of a SYNC output is a transition of
DATACLK either while CS is high or while both CS and R/C
are low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock
while a conversion is occurring can increase the DNL and
Transition Noise.
In Figure 9 a conversion is initiated by taking R/C low with CS
held low. While this condition exists a transition of DATACLK,
clock pulse #0, will enable the generation of a SYNC pulse. Less
then 83 ns after R/C is taken low the BUSY output will go low
to indicate that the conversion process has began. Figure 9
shows R/C then going high and after a delay of greater than
15 ns (t₁₅), clock pulse #1 can be taken high to request the
SYNC output. The SYNC output will appear approximately
50 ns after this rising edge and will be valid on the falling edge
of clock pulse #1 and the rising edge of clock pulse #2. The
MSB will be valid approximately 40 ns after the rising edge of
clock pulse #2 and can be latched off either the falling edge of
clock pulse #2 or the rising edge of clock pulse #3. The LSB
will be valid on the falling edge of clock pulse #17 and the
rising edge of clock pulse #18.
Data should be clocked out during the 1st half of BUSY to
not degrade conversion performance. This requires use of a
10 MHz DATACLK or greater, with data being read out as
soon as the conversion process begins.
EXT
DATACLK
CS
t₁₆
R/C
BUSY
SYNC
DATA
t₁₂
t₁₃
t₁₄
0
1
2
3
t₁₅
t₁
t₂
t₁₇
t₁₂
t₂₀
t₁₈
BIT 15
(MSB)
18
t₁₉
t₁₈
BIT 0
(LSB)
Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion
Using An External Continuous Data Clock (EXT/ INT Set to Logic High)
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REV. A