AD9709_09 Datasheet, PDF (12/32 Pages) Analog Devices – 8-Bit, 125 MSPS, Dual TxDAC+ Digital-to-Analog Converter

AD9709
THEORY OF OPERATION
5V
CLK1/IQCLK CLK2/IQRESET SLEEP
R_SET1
2kΩ
0.1µF
R_SET2
2kΩ
FSADJ1
REFIO
FSADJ2
1.2V REF
GAINCTRL
AVDD
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK
DIVIDER
DAC1
LATCH
DAC2
LATCH
AD9709
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
I_OUTA1
I_OUTB1
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
I_OUTA2
I_OUTB2
MULTIPLEXING LOGIC
WRT1/ CHANNEL 1 LATCH
IQWRT
CHANNEL 2 LATCH
MODE
DVDD1/
DCOM1/ ^DVDD2
DCOM2 ACOM
Mini-Circuits
T1-1T
50Ω
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
50Ω
5V
DVDD1/DVDD2
50Ω
DCOM1/DCOM2
RETIMED CLOCK OUTPUT*
LECROY 9210
PULSE
GENERATOR
PORT 1
DIGITAL
DATA
TEKTRONIX
AWG2021
WITH OPTION 4
PORT 2
WRT2/
IQSEL
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
I_REF1
R_SET1
2kΩ
0.1µF
FSADJ1
REFIO
I_REF2
R_SET2
2kΩ
FSADJ2
1.2V REF
5V
CLK1/IQCLK CLK2/IQRESET
AVDD
SLEEP
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK
DIVIDER
DAC1
LATCH
DAC2
LATCH
I_OUTA1
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
I_OUTB1
I_OUTA2
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
I_OUTB2
AD9709
MULTIPLEXING LOGIC
CHANNEL 1 LATCH CHANNEL 2 LATCH
DVDD1/
DVDD2
ACOM
DCOM1/
DCOM2
V_DIFF = V_OUTA – V_OUTB
V_OUT1A
V_OUT1B
V_OUT2A
R_L1B
50Ω
R_L1A
50Ω
V_OUT2B
R_L2B
5V ^50Ω
R_L2A
50Ω
GAINCTRL
WRT1/
IQWRT
PORT 1
PORT 2
DIGITAL DATA INPUTS
WRT2/
IQSEL
Figure 22. Simplified Block Diagram
MODE
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9709. The
AD9709 consists of two DACs, each one with its own independent
digital control logic and full-scale output current control. Each
DAC contains a PMOS current source array capable of providing
up to 20 mA of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16^th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources instead of an R-2R
ladder enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kΩ).
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching of complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9709 have separate
power supply inputs (that is, AVDD and DVDD1/DVDD2) that
can operate independently over a 3.3 V to 5 V range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
Rev. B | Page 12 of 32