AD8011_15 Datasheet, PDF (12/17 Pages) Analog Devices – 300 MHz Current Feedback Amplifier

AD8011
140
0
120
–40
PHASE
100
–80
80
60
T_O(s)
40
GAIN
–120
–160
–200
20
–240
0
1E+03
1E+04
1E+05 1E+06 1E+07
FREQUENCY (Hz)
1E+08
–280
1E+09
Figure 9. Open-Loop Transimpedance Gain
Note that the ac open-loop plots in Figures 8, 9, and 10 are based
on the full SPICE AD8011 simulations and do not include
external parasitics (see equations below). Nevertheless, these ac
loop equations still provide a good approximation to simulated
and actual performance up to the CLBW of the amplifier. Typi-
cally, g_mc ϫ R1 is –4, resulting in A_O(s) having a right half plane
pole. In the time domain (inverse Laplace of A_O), it appears as
unstable, causing V_O to exponentially rail out of its linear region.
When the loop is closed however, the BW is greatly extended and
the transimpedance gain, T_O (s), overrides and directly controls
the amplifiers stability behavior due to Z_I approaching 1/2 g_mf
for s>>1/τ1 (see Figure 10). This can be seen by the Z_I (s) and
A_V (s) noninverting transfer equations below.
Z_I
(s)
=
(1
–
gmc
×

R1) _{1}
–
Sτ1
gmc ×
R1
2 × gmf (Sτ1 + 1)
+

1

A_V(s) =

¹
+

G
A_O
+
R_F
T_O
G




^{Sτ1}
2
G
gmf
T_O
+
R_F
T_O



+ 1^

400
370
IMPEDANCE
340
20
SERIES 1
0
PHASE
–20
310
–40
280
–60
250
–80
Z_I(s)
220
–100
190
–120
160
–140
SERIES 2
130
–160
100
1E+03
1E+04
1E+05 1E+06 1E+07
FREQUENCY (Hz)
1E+08
–180
1E+09
Figure 10. Open-Loop Inverting Input Impedance
Z_I (s) goes positive real and approaches 1/2 g_mf as ␻ approaches
(g_mc ΄ R1 – 1)/τ1. This results in the input resistance for the A_V (s)
complex term being 1/2 g_mf, the parallel thermal emitter
resistances of Q3/Q4. Using the computed CLBW from A_V (s)
and the nominal design values for the other parameters, results in
a closed-loop 3 dB BW equal to the open-loop corner frequency
(1/2 πτ1) × 1/[G/(2 g_mf ϫ T_O) + R_F/T_O]. For a fixed R_F, the
3 dB BW is controlled by the R_F/T_O term for low gains and
G/(2 g_mf Ï« T_O) for high gains. For example, using nominal design
parameters and R₁ = 1 kΩ (which results in a nominal T_O of
1.2 MΩ), the computed BW is 80 MHz for G = 0 (inverting
I-V mode with R_N removed) and 40 MHz for G = +10/–9.
DRIVING CAPACITIVE LOADS
The AD8011 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, the best
settling response is obtained by the addition of a small series
resistance as shown in Figure 11. The accompanying graph shows
the optimum value for R_SERIES versus capacitive load. It is worth
noting that the frequency response of the circuit when driving
large capacitive loads will be dominated by the passive roll-off
of R_SERIES and C_L.
1k⍀
1k⍀
AD8011
R_SERIES
R_L
1k⍀
C_L
Figure 11. Driving Capacitive Load
REV. C
–11–