AD7723_15 Datasheet, PDF (12/32 Pages) Analog Devices – 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC

AD7723
Pin No.
29
Mnemonic
SYNC
39
DVDD
Description
Synchronization Logic Input. When using more than one AD7723 operated from a common master clock,
SYNC allows each ADC to simultaneously sample its analog input and update its output register. A rising
edge resets the AD7723 digital filter sequencer counter to 0. When the rising edge of CLKIN senses a logic
low on SYNC, the reset state is released. Because the digital filter and sequencer are completely reset
during this action, SYNC pulses cannot be applied continuously.
Digital Power Supply Voltage; 5 V ± 5%.
Table 7. Parallel Mode Pin Function Descriptions
Pin
No. Mnemonic Description
1 DGND/DB2 Data Output Bit.
2 DGND/DB1 Data Output Bit.
3 DGND/DB0 Data Output Bit (LSB).
4
CFMT/RD
Read Logic Input. Used in conjunction with CS to read data from the parallel bus. The output data bus is enabled
when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is sensed high, the output
data bits, DB15 to DB0, are high impedance.
5 DGND/DRDY Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the output data
register. DRDY returns high upon completion of a read operation. If a read operation does not occur between output
updates, DRDY pulses high for two CLKIN cycles before the next output update. DRDY also indicates when
conversion results are available after a SYNC sequence.
30 DVDD/CS
Chip Select Logic Input.
31 DGND/DB15 Data Output Bit (MSB).
32 DGND/DB14 Data Output Bit.
33 SCR/DB13 Data Output Bit.
34 SLDR/DB12 Data Output Bit.
35 SLP/DB11 Data Output Bit.
36 TSI/DB10
Data Output Bit.
37 FSO/DB9
Data Output Bit.
38 SDO/DB8
Data Output Bit.
40 SCO/DB7
Data Output Bit.
41 FSI/DB6
Data Output Bit.
42 SFMT/DB5 Data Output Bit.
43 DOE/DB4
Data Output Bit.
44 DGND/DB3 Data Output Bit.
Rev. C | Page 12 of 32