AD7712_04 Datasheet, PDF (12/28 Pages) Analog Devices – LC2MOS Signal Conditioning ADC

AD7712
Figures 2a and 2b give information similar to that outlined in Table I. In these plots, the output rms noise is shown for the full range
of available cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in these plots
are typical values at 25°C.
10000
1000
100
10
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
1000
100
10
GAIN OF 16
GAIN OF 32
GAIN OF 64
GAIN OF 128
1
1
0.1
10
100
1000
NOTCH FREQUENCY – Hz
10000
Figure 2a. Plot of Output Noise vs. Gain and
Notch Frequency (Gains of 1 to 8)
0.1
10
100
1000
NOTCH FREQUENCY – Hz
10000
Figure 2b. Plot of Output Noise vs. Gain and
Notch Frequency (Gains of 16 to 128)
CIRCUIT DESCRIPTION
The AD7712 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in industrial control or process
control applications. It contains a sigma-delta (or charge-
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter, and a bidirectional
serial communications port.
The part contains two analog input channels, one programmable
gain differential input, and one programmable gain high level
single-ended input. The gain range on both inputs is from 1 to
128. For the AIN1 input, this means that the input can accept
unipolar signals of between 0 mV and 20 mV and 0 mV and
+2.5 V or bipolar signals in the range from ± 20 mV to ± 2.5 V
when the reference input voltage equals 2.5 V. The input volt-
age range for the AIN2 input is ± 4 ϫ V_REF/GAIN and is ± 10 V
with the nominal reference of 2.5 V and a gain of 1. The input
signal to the selected analog input channel is continuously
sampled at a rate determined by the frequency of the master
clock, MCLK IN, and the selected gain (see Table III). A
chargebalancing A/D converter (sigma-delta modulator) converts
the sampled signal into a digital pulse train whose duty cycle
contains the digital information. The programmable gain
function on the analog input is also incorporated in this sigma-
delta modulator with the input sampling frequency being
modified to give the higher gains. A sinc³ digital low-pass filter
processes the output of the sigma-delta modulator and updates
the output register at a rate determined by the first notch
frequency of this filter. The output data can be read from the
serial port randomly or periodically at any rate up to the output
register update rate. The first notch of this digital filter (and
therefore its –3 dB frequency) can be programmed via an on-chip
control register. The programmable range for this first notch
frequency is from 9.76 Hz to 1.028 kHz, giving a programmable
range for the –3 dB frequency of 2.58 Hz to 269 Hz.
The basic connection diagram for the part is shown in Figure 3.
This shows the AD7712 in the external clocking mode with both
the AV_DD and DV_DD pins of the AD7712 being driven from the
analog 5 V supply. Some applications will have separate supplies
for both AV_DD and DV_DD, and in some of these cases, the analog
supply will exceed the 5 V digital supply (see the Power Supplies
and Grounding section).
ANALOG
5V SUPPLY
10␮F
0.1␮F
0.1␮F
DIFFERENTIAL
ANALOG INPUT
SINGLE-ENDED
ANALOG INPUT
DV_DD
ANALOG
GROUND
DIGITAL
GROUND
AV_DD DV_DD
DRDY
AIN1(+)
TFS
AIN1(–)
RFS
AIN2 _AD7712
SDATA
STANDBY
SCLK
AGND
V_SS
DGND
REF OUT
REF IN(+)
V BIAS
A0
MODE
SYNC
MCLK OUT
REF IN(–)
MCLK IN
DATA
READY
TRANSMIT
(WRITE)
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
ADDRESS
INPUT
5V
Figure 3. Basic Connection Diagram
–12–
REV. F