AD7124-4 Datasheet, PDF(12/90 Page) Analog Devices – 4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference

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AD7124-4 Datasheet, PDF (12/90 Pages) Analog Devices – 4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference

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AD7124-4

CS (I)

DOUT/RDY (O)

MSB

LSB

t7A

SCLK (I)

I = INPUT, O = OUTPUT

Figure 4. Read Cycle Timing Diagram (CS_EN Bit Set)

DIN

DOUT/RDY

CS (I)

t11

SCLK (I)

DIN (I)

t10

MSB

LSB

I = INPUT, O = OUTPUT

Figure 5. Write Cycle Timing Diagram

t12

WRITE

t12

READ

SCLK

Figure 6. Delay Between Consecutive Serial Operations

Data Sheet

DIN

t13

DOUT/RDY

SCLK

Figure 7. DOUT/RDY High Time when DOUT/RDY is Initially Low and the Next Conversion is Available

SYNC (I)

t14

MCLK (I)

Figure 8. SYNC Pulse Width

Rev. A | Page 12 of 90

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