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AD1887 Datasheet, PDF (12/16 Pages) Analog Devices – AC’97 SoundMAX Codec
AD1887
General Purpose Register (Index 20h)
Reg
Num
Name
20h General Purpose
D15 D14 D13 D12 D11 D10 D9 D8 D7
D6 D5 D4 D3 D2 D1 D0 Default
X X X X X X X X LPBK X X X X X X X 0000h
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default
value is 0000h, which is all off.
LPBK
Loopback Control. ADC/DAC digital loopback mode.
Subsection Ready Register (Index 26h)
Reg
Num
Name
26h Power-Down Cntrl/Stat
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
X PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC NA
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the
AD1887 subsections. If the bit is a one, that subsection is “ready.” Ready is defined as the subsection able to perform in its nomi-
nal state.
ADC
ADC section ready to transmit data.
DAC
DAC section ready to accept data.
ANL
Analog gainuators, attenuators, and mixers ready.
REF
PR[5:0]
Voltage References, VREF and VREFOUT up to nominal level.
AD1887 Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot be
powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until
the reference is up.
PR0 – Powered-Down ADC
PR1 – Powered-Down DAC
PR2 – Powered-Down Analog Mixer
PR3 – Powered-Down VREF and VREFOUT
PR4 – Powered-Down AC-Link
PR5 – Powered-Down Internal Clock
PR6 – Powered-Down Headphone
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can
be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are
both set.
In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in
the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect or disable PR5.
Power-Down State
PR6 PR5 PR4 PR3 PR2 PR1 PR0
ADC Power-Down
0
0
0
0
0
0
1
DACs Power-Down
0
0
0
0
0
1
0
ADC and DAC Power-Down
0
0
0
0
0
1
1
Mixer Power-Down
0
0
0
0
1
0
0
ADC + Mixer Power-Down
0
0
0
0
1
0
1
DAC + Mixer Power-Down
0
0
0
0
1
1
0
ADC + DAC + Mixer Power-Down 0
0
0
0
1
1
1
Standby
1
1
1
1
1
1
1
–12–
REV. 0