AD1857JRSZ Datasheet, PDF (12/16 Pages) Analog Devices – Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs

AD1857/AD1858
Control Signals
The MODE and DEEMP control inputs are normally connected
HI or LO to establish the operating state of the AD1857/AD1858.
They can be changed dynamically (and asynchronously to the
LRCLK and the master clock) as long as they are stable before
the first serial data input bit (i.e., the MSB) is presented to the
AD1857/AD1858.
APPLICATION ISSUES
Interface to MPEG Audio Decoders
Figure 15 shows the suggested interface to the Analog Devices
ADSP-21xx family of DSP chips, for which several MPEG
audio decode algorithms are available. The ADSP-21xx
supports 16 bits of data using a left-justified DSP serial port
style format.
SCLK
RFS
NC
TFS
ADSP-21xx
DT
DR
NC
NC = NO CONNECT
19 BCLK
18 LRCLK
20 SDATA
AD1858
HI 3 MODE
HI 6 384/256
1 MCLK
Figure 15. Interface to ADSP-21xx
Figure 16 shows the suggested interface to the Texas Instruments
TMS320AV110* MPEG audio decoder IC. The TMS320AV110
supports 18 bits of data using a right-justified output format.
SCLK
TMS320AV110
LRCLK
PCMDATA
PCMCLK
19 BCLK
18 LRCLK
20 SDATA
AD1858
HI 3 MODE
HI 6 _384/256
256 x Fs
1 MCLK
Figure 16. Interface to TMS320AV110
Figure 17 shows the suggested interface to the LSI Logic
L64111* MPEG audio decoder IC. The L64111 supports 16
bits of data using a left-justified output format.
Figure 18 shows the suggested interface to the Philips SAA2500*
MPEG audio decoder IC. The SAA2500 supports 18 bits of
data using an I²S-compatible output format.
SCK
WS
SAA2500
SD
FSCLKIN
19 BCLK
18 LRCLK
20 SDATA
AD1857
HI 3 MODE
HI 6 384/256
1 MCLK
256 x Fs
Figure 18. Interface to SAA2500
Figure 19 shows the suggested interface to the Zoran ZR38000*
DSP chip, which can act as an MPEG audio or AC-3 audio
decoder. The ZR38000 supports 16 bits of data using a left-
justified output format.
SCKB
ZR38000
WSB
SDB
SCKIN
19 ^BCLK
18 LRCLK
20 SDATA
AD1857
LO 3 MODE
HI 6 384/256
1 MCLK
256 x Fs
Figure 19. Interface to ZR38000
Figure 20 shows the suggested interface to the C-Cube
Microsystems CL480* MPEG system decoder IC. The CL480
supports 16 bits of data using a right-justified output format.
CL480
DA-BCK
DA-LRCK
19 BCLK
18 LRCLK
DA-DATA
DA-XCK
20 SDATA
AD1858
HI 3 MODE
HI 6 384/256
1 MCLK
256 x Fs
Figure 20. Interface to CL480
SCLKO
LRCLKO
L64111
SERO
19 BCLK
18 LRCLK
20 SDATA
SYSCLK
LO 3 MODE
LO 6 384/256
1 MCLK
384 x Fs
Figure 17. Interface to L64111
AD1857
*All trademarks are properties of their respective holders.
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