AD10265_15 Datasheet, PDF (12/24 Pages) Analog Devices – Dual Channel, 12-Bit, 65 MSPS A/D Converter

AD10265
J1
A_INB3
AGNDB
J2
A_INB2
AGNDB
J22
A_INB1
AGNDB
J7
A_INA3
AGNDA
J8
A_INA2
AGNDA
J20
A_INA1
AGNDA
C57
0.1␮F
JP5
CLKLATCHB2
CLKLATCHB1
JP3
DRBOUT
DRAOUT
JP4
CLKLATCHA1
JP6
CLKLATCHA2
U2:A
U2:D
U2:B ^JP1
1
13
3
11 ⁴
6
2
12
5
74LCX00M 74LCX00M 74LCX00M
U4:A
U4:D
U4:B
1
13
3
11 ⁴
6
2
12
5
74LCX00M 74LCX00M 74LCX00M _JP2
LATCHB
BUFLATB
BUFLATA
LATCHA
–5.2VAB
C59
10␮F
AGNDB
47⍀
AT 100MHz
L9
47
47⍀
AT 100MHz
L8
47
+5VAB
C52
10␮F
AGNDB
–5.2VAA
L10
C22
47
10␮F
AGNDA
+5VAA
L7
C53
10␮F
47
47⍀
AT 100MHz
AGNDA
AGNDA
AV_EE
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
10
AGNDA
11
AGNDA
12
NC
13
14 ^AVEE
15 ^AVEE
NC
16
NC
17
D0A(LSB)
18
D1A
19
D2A
20
D3A
21
D4A
22
D5A
23
D6A
24
D7A
25
D8A
26
DGNDA
U1
AD10265
60
GNDB
59
GNDB
58
GNDB
57
NC
56
NC
55
NC
54
GNDB
53
GNDB
52
ENCBB
51
ENCB
50
DV_{CC 49}
D11B(MSB)
48
D10B
47
D9B
46
D8B
45
D7B
44
GNDB
C61
0.1␮F
DRBOUT
AGNDB
ENCBB
ENCB
DUT 3.3VDB
D13B(MSB) _C64
D12B
0.1␮F
D11B
D10B
D9B
AGNDB
+3.3VDB
L6
47
C58
10␮F
DGNDB
DGNDA
DGNDB
NC = NO CONNECT
+3.3VDA
L11
C62
47
10␮F
C63
0.1␮F
DGNDA
DGNDA
DUT 3.3VDB _SPARE
GATE
C26
0.1␮F
U2:C
10
8
9
DGNDB
74LCX00M
DUT 3.3VDA _SPARE
GATE
C27
0.1␮F
U4:C
10
8
9
DGNDA
74LCX00M
DGNDB
DGNDA
Figure 13a. Evaluation Board Schematic
–12–
REV. A