SSM2220SZ Datasheet, PDF (11/12 Pages) Analog Devices – Audio Dual Matched PNP Transistor

Data Sheet
by consulting Figure 15. Typical output impedance levels approach
the performance of a perfect current source.
(ro)Q3 =
1
= 1 MΩ
1.0 μMho
Q2 and Q3 are in series and operate at the same current level;
therefore, the total output impedance is as follows:
RO = hFE × (ro)Q3 ≈ (160)(1 MΩ) = 160 MΩ
Current Matching
The objective of current source or mirror design is generation
of currents that either are matched or must maintain a constant
ratio. However, mismatch of base emitter voltages causes output
current errors. Consider the example of Figure 21.
I_C
+
ΔI_C
2
I_C
–
ΔI_C
2
–
A CLOSELY MATCHED
TRANSISTOR PAIR
V_B
R1
R2
+
R1 = R2 = R
Figure 21. Current Matching Circuit
SSM2220
If the resistors and transistors are equal and the collector
voltages are the same, then the collector currents match precisely.
Investigating the current matching errors resulting from a nonzero
VOS, ΔIC is defined as the current error between the two transistors.
Figure 22 describes the relationship of current matching errors
vs. offset voltage for a specified average current, IC. Note that
because the relative error between the currents is exponentially
proportional to the offset voltage, tight matching is required to
design high accuracy current sources. For example, if the offset
voltage were 5 mV at 100 μA collector current, the current match-
ing error would be 20%. Additionally, temperature effects, such
as offset drift (3 μV/°C per mV of VOS), degrade performance if
Q1 and Q2 are not well matched.
1.2
I_C = 10µA
I_C = 100µA
1.0
0.8
SSM2220 V_OS
PERFORMANCE
0.6
0.4
0.2
0
0.001
0.01
0.1
V_OS (mV)
I_C = 1mA
R = 3kΩ
h_FE = 200
I_C
=
I_C1
+
2
I_C2
ΔI = I_C1 – I_C2
1
10
Figure 22. Current Matching Accuracy vs. Offset Voltage
Rev. C | Page 11 of 12