OP176_15 Datasheet, PDF (11/21 Pages) Analog Devices – Bipolar/JFET, Audio Operational Amplifier

OP176
Attention to Source Impedances Minimizes Distortion
Since the OP176 is a very low distortion amplifier, careful
attention should be given to source impedances seen by both
inputs. As with many FET-type amplifiers, the p-channel
JFETs in the OP176’s input stage exhibit a gate-to-source
capacitance that varies with the applied input voltage. In an
inverting configuration, the inverting input is held at a virtual
ground and, as such, does not vary with input voltage. Thus,
since the gate-to-source voltage is constant, there is no distor-
tion due to input capacitance modulation. In noninverting
applications, however, the gate-to-source voltage is not
constant. The resulting capacitance modulation can cause
distortion above 1 kHz if the input impedance is > 2 kΩ and
unbalanced.
Figure 36 shows some guidelines for maximizing the distortion
performance of the OP176 in noninverting applications. The
best way to prevent unwanted distortion is to ensure that the
parallel combination of the feedback and gain setting resistors
(R_F and R_G) is less than 2 kΩ. Keeping the values of these
resistors small has the added benefits of reducing the thermal
noise of the circuit and dc offset errors. If the parallel combina-
tion of R_F and R_G is larger than 2 kΩ, then an additional
resistor, R_S, should be used in series with the noninverting
R_G
R_F
R_S*
OP176
V_OUT
V_IN
* R_S = R_G//R_F IF R_G//R_F > 2kΩ
FOR MINIMUM DISTORTION
Figure 36. Balanced Input Impedance to Mininize
Distortion in Noninverting Amplifier Circuits
input. The value of R_S is determined by the parallel combina-
tion of R_F and R_G to maintain the low distortion performance of
the OP176. For a more generalized treatment on circuit
impedances and their effects on circuit distortion, please review
the section on Active Filters at the end of the Applications
section.
Driving Capacitive Loads
As with any high speed amplifier, care must be taken when
driving capacitive loads. The graph in Figure 14 shows the
OP176’s overshoot versus capacitive load. The test circuit is a
standard noninverting voltage follower; it is this configuration
that places the most demand on an amplifier’s stability. For
capacitive loads greater than 400 pF, overshoot exceeds 40%
and is roughly equivalent to a 45° phase margin. If the applica-
tion requires the OP176 to drive loads larger than 400 pF, then
external compensation should be used.
Figure 37 shows a simple circuit which uses an in-the-loop
compensation technique that allows the OP176 to drive any
capacitive load. The equations in the figure allow optimization
of the output resistor, R_X, and the feedback capacitor, C_F, for
optimal circuit stability. One important note is that the circuit
bandwidth is reduced by the feedback capacitor, C_F, and is
given by:
BW = ¹
2 π R F CF
R_G
V_IN
R_F
C_F
R_X
OP176
V_OUT
C_L
R_X = R_O R_G WHERE R_O = OPEN-LOOP OUTPUT RESISTANCE
R_F
[ ] ( ) ^I
C_F =
I+
| A_CL|
( ) RF + RG
R_F
C_L R_O
Figure 37. In-the-Loop Compensation Technique for
Driving Capacitive Loads
APPLICATIONS USING THE OP176
A High Speed, Low Noise Differential Line Driver
The circuit of Figure 38 is a unique line driver widely used in
many applications. With ± 18 V supplies, this line driver can
deliver a differential signal of 30 V p-p into a 2.5 kΩ load. The
high slew rate and wide bandwidth of the OP176 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 15 nV/√Hz. The circuit is capable of driving lower
impedance loads as well. For example, with a reduced output
level of 5 V rms (14 V p-p), the circuit exhibits a full-power
bandwidth of 190 kHz while driving a differential load of 249 Ω!
The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
importance. Like the transformer-based design, either output
can be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can
be set according to the equation in the diagram. This allows the
design to be easily set for noninverting, inverting, or differential
operation.
R1
2kΩ
V_{IN 3}
6
2 ^A1
R2
2kΩ
R3
2kΩ
2
R9
6
50Ω
3 ^A2
R7
2kΩ
R4
2kΩ
R5
2kΩ _R6
2kΩ
2
R10
6
50Ω
3 ^A3
R8
2kΩ
V_O1
R11
1kΩ
P1
10kΩ
V_O2 – V_O1 = V_IN
R12
1kΩ
V_O2
A1, A2, A3 = OP176
GAIN = ^R3
R1
SET R2, R4, R5 = R1 AND R6, R7, R8 = R3
Figure 38. A High Speed, Low Noise Differential Line
Driver
REV. 0
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