ADV7842KBCZ-5 Datasheet, PDF (11/28 Pages) Analog Devices – Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics igitizer and 3D Comb Filter Decoder

ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
AVDD to GND
VDD to GND
PVDD to GND
DVDDIO to GND
VDD_SDRAM to GND
CVDD to GND
TVDD to GND
AVDD to PVDD
AVDD to VDD
TVDD to CVDD
DVDDIO to VDD_SDRAM
VDD_SDRAM to AVDD
VDD_SDRAM to VDD
Digital Inputs Voltage to GND
Digital Outputs Voltage to GND
5 V Tolerant Digital Inputs to GND¹
Analog Inputs to GND
XTALN and XTALP to GND
Maximum Junction Temperature
(TJ MAX)
Storage Temperature Range
Infrared Reflow Soldering (20 sec)
Rating
2.2 V
2.2 V
2.2 V
4.0 V
4.0 V
2.2 V
4.0 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +2.2 V
−0.3 V to +3.3 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to DVDDIO + 0.3 V
−0.3 V to DVDDIO + 0.3 V
5.5 V
−0.3 V to AVDD + 0.3 V
−0.3 V to PVDD + 0.3 V
125°C
−65°C to +150°C
260°C
1 _{The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI5,}
HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, DDCA_SCL, DDCA_SDA, DDCB_SCL
and DDCB_SDA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ADV7842
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the ADV7842, the
user is advised to turn off unused sections of the part.
Due to PCB metal variation, and therefore variation in PCB
heat conductivity, the value of θJA may differ for various PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the JA θvalue.
The maximum junction temperature (TJ MAX) of 125°C must not be
exceeded. The following equation calculates the junction tempera-
ture using the measured package surface temperature and applies
only when no heat sink is used on the device under test (DUT):
( ) T_J = T_S + Ψ _JT ×W_TOTAL
where:
TS is the package surface temperature (°C).
ΨJT = 0.5°C/W for the 256-ball BGA.
WTOTAL = (PVDD × IPVDD) + (0.4 × TVDD × ITVDD) +
(CVDD × ICVDD) + (AVDD × IAVDD) + (VDD × IVDD) +
(A × DVDDIO × IDVDDIO) + (VDD_SDRAM × I ) VDD_SDRAM
where:
0.4 reflects the 40% of TVDD power that is dissipated on the
part itself.
A = 0.5 when the output pixel clock is >74 MHz.
A = 0.75 when the output pixel clock is ≤74 MHz.
ESD CAUTION
Rev. B | Page 11 of 28