ADV473_15 Datasheet, PDF (11/12 Pages) Analog Devices – CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC

ADV473
PC BOARD LAYOUT CONSIDERATIONS
The layout should be optimized for lowest noise on the ADV473
power and ground lines by shielding the digital inputs and pro-
viding good decoupling. The lead length between groups of V_AA
and GND pins should be minimized so as to minimize inductive
ringing.
Ground Planes
The ground plane should encompass all ADV473 ground pins,
current/voltage reference circuitry, power supply bypass circuitry
for the ADV473, the analog output traces, and all the digital sig-
nal traces leading up to the ADV473.
Power Planes
The ADV473 and any associated analog circuitry should have its
own power plane, referred to as the analog power plane. This
power plane should be connected to the regular PCB power
plane (V_CC) at a single point through a ferrite bead, as illustrated
in Figures 7 and 8. This bead should be located within three
inches of the ADV473.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV473 power pins and voltage reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable opera-
tion, to reduce the lead inductance. Best performance is ob-
tained with a 0.1 µF ceramic capacitor decoupling each of the
two groups of V_AA pins to GND. These capacitors should be
placed as close as possible to the device.
It is important to note that while the ADV473 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise and should consider using a three-terminal voltage regula-
tor for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV473 should be isolated as much as
possible from the analog outputs and other analog circuitry.
Also, these input signals should not overlay the analog power
plane.
Due to the high clock rates involved, long clock lines to the
ADV473 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V_CC), and not to the
analog power plane.
0.1µF
0.1µF
POWER SUPPLY DECOUPLING
(0.1µF CAPACITOR FOR
EACH V_REF GROUP)
+5V (V_AA)
0.1µF
ANALOG POWER PLANE
V_AA
+5V (V_AA)
10µF
COMP
COMP
V_REFOUT
V_REFIN
ADV473
+5V (V_AA)
1kΩ
(1% METAL)
AD589
(1.2 V_REF )
0.1µF
R_SET
140Ω
R_SET
IOR
IOG
IOB
GND
75Ω
CO-AXIAL CABLE
(75Ω)
75Ω
75Ω
75Ω
75
Ω
75Ω
BNC
CONNECTORS
L1
(FERRITE
BEAD)
+5V (V_CC)
0.1µF
MONITOR
(CRT)
COMPONENT
C1 – C5
C6
L1
R1, R2, R3
R4
R_SET
Z1
DESCRIPTION
VENDOR PART NUMBER
0.1µF CERAMIC CAPACITOR
10µF TANTALUM CAPACITOR
FERRITE BEAD
75Ω 1% METAL FILM RESISTOR
1kΩ 5% RESISTOR
1% METAL FILM RESISTOR
ERIE RPE112Z5U104M50V
MALLORY CSR13G106KM
FAIR-RITE 2743001111
1.23V VOLTAGE REFERENCE AD589JN
Figure 7. Typical Connection Diagram (External Voltage
Reference)
REV. A
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