ADV202_15 Datasheet, PDF (11/40 Pages) Analog Devices – JPEG2000 Video Codec

Data Sheet
ADV202
DREQ/DACK ^{DMA MODE—SINGLE FIFO READ OPERATION}
Table 7.
Parameter
Description
Min
DREQ_PULSE
DREQ Pulse Width¹
1
t
DREQ
DACK Assert to Subsequent DREQ Delay
2.5
t_RDSU
RD to DACK Setup
0
t
DACK to Data Valid
2.5
RD
t_HD
Data Hold
1.5
DACK_LO
DACK Assert Pulse Width
2
DACK_HI
DACK Deassert Pulse Width
2
t_RDHD
RD Hold After DACK Deassert
0
RDFSRQ
RD Assert to FSRQ Deassert (FIFO Empty)
1.5
t_DREQRTN
DACK to DREQ Deassert (DR × PULS = 0)
2.5
1 _{Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a nonzero value.}
2 _{For a definition of JCLK, see the PLL section.}
DREQ_PULSE
t_DREQ
DREQ
DACK_LO
DACK_HI
DACK
RD
HDATA
t_RDSU
t_RD
t_HD
0
1
Typ Max
15
3.5 × JCLK + 7.5 ns
11
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
t_RDHD
2
Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000)
Unit
JCLK cycles²
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
ns
JCLK cycles
JCLK cycles
DREQ
DACK
RD
HDATA
t_DREQRTN
DACK_LO
DACK_HI
t_RDSU
t_RDHD
t_RD
t_HD
0
1
2
Figure 10. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
Rev. D | Page 11 of 40