ADG888 Datasheet, PDF (11/16 Pages) Analog Devices – 0.4 OHM CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP Packages

TERMINOLOGY
IDD
Positive supply current.
VD (VS)
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
ΔRON
On resistance match between any two channels.
IS (OFF)
Source leakage current with the switch off.
ID, IS (ON)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (OFF)
Off switch source capacitance. Measured with reference to
ground.
CD, CS (ON)
On switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tON
Delay time between the 50% and the 90% points of the digital
input and switch on condition.
ADG888
tOFF
Delay time between the 50% and the 90% points of the digital
input and switch off condition.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during on-off switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance. This is
specified for two conditions:
• Adjacent channel, that is, S1A to S2A, S1B to S2B, S3A to
S4A, or S3B to S4B.
• Adjacent switch, that is, S1A to S1B, S2A to S2B, S3A to
S3B, or S4A to S4B.
−3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitudes plus signal noise to the
fundamental.
Rev. A | Page 11 of 16