ADG701_06 Datasheet, PDF (11/12 Pages) Analog Devices – CMOS Low Voltage 2 Ω SPST Switches

OUTLINE DIMENSIONS
3.00
BSC
8
3.00
BSC
1
5
4.90
BSC
4
PIN 1
0.65 BSC
0.15
1.10 MAX
0.00
0.38
0.22
0.80
0.23
0.08
8°
0°
0.60
0.40
COPLANARITY SEATING
0.10
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 20. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.90 BSC
1.60 BSC
PIN 1
INDICATOR
1.30
1.15
0.90
0.15 MAX
6
5
4
1
2
3
2.80 BSC
1.90
BSC
0.95 BSC
1.45 MAX _0.22
0.08
0.50
0.30
SEATING
PLANE
10°
0.60
4°
0.45
0°
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 21. 6-Lead Small Outline Transistor Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
ADG701/ADG702
Rev. C | Page 11 of 12