AD9953 Datasheet, PDF (11/42 Pages) Analog Devices – 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer

PRELIMINARY TECHNICAL DATA
AD9953
In certain applications it is desirable to force the output signal to ZERO phase. Simply setting the
FTW to 0 does not accomplish this. It only results in the DDS core holding its current phase value.
Thus, a control bit is required to force the Phase Accumulator output to zero.
At power up the Clear Phase Accumulator bit is set to logic one but the buffer memory for this bit
is cleared (logic zero). Therefore, upon power up, the phase accumulator will remain clear until the
first I/O UPDATE is issued.
Phase Truncation
The 32-bit phase values generated by the Phase Accumulator are truncated to 19 bits prior to the
COS(x) block. That is, the 19 most significant bits of phase are retained for subsequent
processing. This is typical of standard DDS architecture and is a trade off between hardware
complexity and spurious performance. It can be shown that 19-bit phase resolution is sufficient to
yield 14-bit amplitude resolution with an error of less than ½ LSB. The decision to truncate at 19
bits of phase guarantees the phase error of the COS(x) block to be less than the phase error
associated with the amplitude resolution of the 14-bit DAC.
Clock Input
The AD9953 supports various clock methodologies. Support for differential or single-ended input
clocks, enabling of an on-chip oscillator and/or phase-locked loop (PLL) multiplier are all
controlled via user programmable bits. The AD9953 may be configured in one of six operating
modes to generate the system clock. The modes are configured using the ClkModeSelect pin,
CFR1<4>, and CFR2<7:3>. Connecting the external pin ClkModeSelect to logic HIGH enables
the on-chip crystal oscillator circuit. With the on-chip oscillator enabled, users of the AD9953
connect an external crystal to the REFCLK and REFCLKB inputs to produce a low frequency
reference clock in the range of 20-30MHz. The signal generated by the oscillator is buffered before
it is delivered to the rest of the chip. This buffered signal is available via the crystal out pin. Bit
CFR1<4> can be used to enable or disable the buffer, turning on or off the system clock. The
oscillator itself is not powered down in order to avoid long start-up times associated with turning
on a crystal oscillator. Writing bit CFR2<1> to logic HIGH enables the crystal oscillator output
buffer. Logic LOW at CFR2<1> disables the oscillator output buffer.
Connecting ClkModeSelect to logic LOW disables the on-chip oscillator and the oscillator output
buffer. With the oscillator disabled an external oscillator must provide the REFCLK and/or
REFCLKB signals. For differential operation these pins are driven with complementary signals.
For single-ended operation a 0.1uF capacitor should be connected between the unused pin and the
positive power supply. With the capacitor in place the clock input pin bias voltage is 1.35V. In
addition, the PLL may be used to multiply the reference frequency by an integer value in the range
of the 4 to 20.
REV. PrB 1/30/03
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Analog Devices, Inc.