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AD9644-80KITZ Datasheet, PDF (11/44 Pages) Analog Devices – 14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual Serial Output Analog-to-Digital Converter (ADC)
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9644
VCMB 1
AVDD 2
DNC 3
AVDD 4
CLK+ 5
CLK– 6
AVDD 7
SYNC 8
AVDD 9
DRGND 10
DRVDD 11
DNC 12
AD9644
TOP
VIEW
(Not to Scale)
36 VCMA
35 DNC
34 DNC
33 PDWN
32 DNC
31 CSB
30 SCLK
29 SDIO
28 DRVDD
27 DRVDD
26 DRGND
25 DNC
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. LFCSP Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
ADC Power Supplies
11, 15, 22, 27, 28
DRVDD
2, 4, 7, 9, 37, 38, 41, AVDD
42, 43, 44, 47, 48
3, 12, 25, 32, 34, 35 DNC
10, 16, 21, 26
DRGND
0
AGND,
Exposed Pad
ADC Analog
40
39
45
46
36
1
5
6
Digital Input
8
24
VIN+A
VIN−A
VIN+B
VIN−B
VCMA
VCMB
CLK+
CLK−
SYNC
DSYNC+A
23
DSYNC−A
14
DSYNC+B
13
DSYNC−B
Type
Supply
Supply
Driver
Ground
Ground
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect.
Digital Driver Supply Ground.
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for
proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Channel A Analog Input.
Common-Mode Level Bias Output for Channel B Analog Input.
ADC Clock Input—True.
ADC Clock Input—Complement.
Input Clock Divider Synchronization Pin.
Active Low JESD204A LVDS Channel A SYNC Input—True/JESD204A CMOS
Channel A SYNC Input.
Active Low JESD204A LVDS Channel A SYNC Input—Complement.
Active Low JESD204A LVDS Channel B SYNC Input—True/JESD204A CMOS
Channel A SYNC Input.
Active Low JESD204A LVDS Channel B SYNC Input—Complement.
Rev. C | Page 11 of 44