AD8044ANZ Datasheet, PDF (11/16 Pages) Analog Devices – Quad 150 MHz Rail-to-Rail Amplifier

AD8044
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 33, the AD8044 recovers
within 50 ns from negative overdrive and within 25 ns from
positive overdrive.
V_S = +5V
A_V = +2
R_F = 2k⍀
R_L = 2k⍀
V_IN
2V/DIV
V_OUT
1V/DIV
2V 1V
50ns
Figure 33. Overdrive Recovery, VS + 5 V, V_IN = 4 V Step
Circuit Description
The AD8044 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process which
enables the construction of PNP and NPN transistors with
similar f_Ts in the 2 GHz–4 GHz region. The process is dielectri-
cally isolated to eliminate the parasitic and latch-up problems
caused by junction isolation. These features allow the construc-
tion of high frequency, low distortion amplifiers with low supply
currents. This design uses a differential output input stage to
maximize bandwidth and headroom (see Figure 34). The
smaller signal swings required on the first stage outputs (nodes
S1P, S1N) reduce the effect of nonlinear currents due to
junction capacitances and improve the distortion performance.
With this design harmonic distortion of better than –85 dB
@ 1 MHz into 100 W with V_OUT = 2 V p-p (Gain = +2) on a
single 5 volt supply is achieved.
The AD8044’s rail-to-rail output range is provided by a comple-
mentary common-emitter output stage. High output drive capa-
bility is provided by injecting all output stage predriver currents
directly into the bases of the output devices Q8 and Q36. Bias-
ing of Q8 and Q36 is accomplished by I8 and I5, along with a
common-mode feedback loop (not shown). This circuit topol-
ogy allows the AD8044 to drive 50 mA of output current with
the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from –0.2 V
below the negative rail to within 1.2 V of the positive rail. Ex-
ceeding these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
Driving Capacitance Loads
The capacitive load drive of the AD8044 can be increased by
adding a low valued resistor in series with the load. Figure 35
shows the effects of a series resistor on capacitive drive for vary-
ing voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less over-
shoot. Adding a series resistor with lower closed-loop gains
accomplishes this same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and capacitive load.
V_CC
V_INP
V_INN
I1
R26
Q4
I10
R39
Q5
R15 R2
Q13 Q17
Q40
V_EE
I2 I3 _Q25
Q50
I9
Q36
Q51 ^Q39
Q23
I5
V_EE
Q22
R23 R27
Q7
Q31
Q21 Q27
C3
V_OUT
SIP
SIN
C9
Q2
Q11
Q3
Q24
C7
V_EE
R5
R21 R3
I7
Q47
I11
Q8
I8
V_CC
Figure 34. AD8044 Simplified Schematic
REV. B
–11–