AD7466 Datasheet, PDF (11/15 Pages) Analog Devices – 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23

pecifications
AD7466/AD7467/AD7468
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TITLE
Figure 13. THD vs. Analog Input Frequency for Various
Source Impedance
Digital Inputs
The digital inputs applied to the AD7466/AD7467/
AD7468 are not limited by the maximum ratings which
limit the analog inputs. One advantage of SCLK and CS
not being restricted by the V_DD + 0.3V limit is the fact that
power supply sequencing issues are avoided. If CS or
SCLK are applied before V_DD then there is no risk of
latch-up as there would be on the analog inputs if a signal
greater than 0.3V was applied prior to V_DD.
MODE OF OPERATION
The AD7466/AD7467/AD7468 automatically enters
powerdown at the end of each conversion. This mode of
operation is designed to provide flexible power manage-
ment options and to optimize the power dissipation/
throughput rate ratio for differing application require-
ments. Figure 14 shows the general diagram of the
operaion of the AD7466/AD7467/AD7468. On the falling
CS edge the part begins to power up and the Track and
Hold, which was in Hold while the part was in power
down, will go into track mode. When operating the part
with a 2.4 MHz clock it will take 2 clock cycles to fully
power up the part and acquire the input signal. On the
third SCLK falling edge after the CS falling edge the
Track and Hold will return to hold mode. For the
AD7466 sixteen serial clock cycles are required to com-
plete the conversion and access the complete conversion
result.On the 16th SCLK falling edge the part will auto-
matically enter power down . The AD7467 will automati-
cally enter powerdown on the fourteenth SCLK falling
edge. The AD7468 will automatically enter powerdown
on the twelveth SCLK falling edge. When supplies are
first applied to the AD7466/AD7467/AD7468 a dummy
conversion should be performed to ensure that the part is
in powerdown mode.
The conversion is iniated on the falling edge of CS as
described in the Serial Interface section. For the AD7466
if CS is brought high any time before the 16th SCLK
falling edge the part will enter power down and the con-
version that was initiated by the falling edge of CS will be
terminated and SDATA will go back into tri-state. This
also applies for the AD7467/AD7468, if CS is brought
high before the conversion is complete (the 14th SCLK
falling edge for the AD7467, and the 12th SCLK falling
edge for the AD7468) the part will enter powerdown and
the conversion will be terminated.
Once a data transfer is complete (SDATA has returned to
tri-state), another conversion can be initiated after the
quiet time, t_quiet, has elapsed by bringing CS low again.
REV. PrC
THE PART BEGINS
TO POWER UP
123
AD7468 ENTERS AD7467 ENTERS
POWERDOWN POWERDOWN AD7466 ENTERS
POWERDOWN
12 14 16
VALID DATA
Figure 14. Normal Mode Operation
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