AD664JPZ Datasheet, PDF (11/23 Pages) Analog Devices – Monolithic 12-Bit Quad DAC

AD664
Fully transparent operation can be thought of as a simultaneous
load of data from Figure 9a where replacing LS with TR causes
all 4 DACs to be loaded at once.
The Fully transparent mode is achieved by asserting lows on
QS0, QS1, QS2, TR and CS while keeping LS high in addition
to MS and RB. Figure 18a illustrates the necessary timing rela-
tionships. Fully transparent operation will also work with TR
tied low (enabled).
1
LS
DATA INPUT/
OUTPUT BITS
QS
TR
CS
t _DS
t_QS
t _TS
DATA VALID
t_TW
t _CH
t _DH
t_QH
Figure 18a. Fully Transparent Mode
OUTPUT DATA
Two types of outputs may be obtained from the internal data
registers of the AD664 chip, mode select and DAC input code
data. Readback data may be in the same forms in which it can
be entered; 4-, 8-, and 12-bit wide words (12 bits only for
28-pin versions).
DAC Data Readback
DAC input code readback data is obtained by setting the address
of the DAC (DS0, DS1) and Quads (QS0, QS1, QS2) on the
address pins and bringing the RD and CS pins low. The timing
diagram for a DAC code readback operation appears in Figure 20.
SYMBOL
25؇C
MIN (ns)
T_MIN to T_MAX
MIN (ns)
t_AS
0
0
t_QS
0
0
t_TS*
0
0
t_TW
80
90
t_CH
90
110
t_DH
0
0
t_QH
0
0
*FOR t_TS > 0, THE WIDTH OF TR MUST BE
INCREASED BY THE SAME AMOUNT THAT
t_TS IS GREATER THAN 0 ns.
Figure 18b. Fully Transparent Mode Timing
Partially transparent operation can be thought of as preloading
the first rank in Figure 10a without requiring the additional CS
pulse from Figure 11.
The partially transparent mode is achieved by setting CS, QS0,
QS1, QS2, LS, and TR low while keeping RD and MS high.
The address of the transparent DAC is asserted on DS0 and
DS1. Figure 19a illustrates the necessary timing relationships.
Partially transparent operation will also work with TR tied low
(enabled).
DATA INPUT/
OUTPUT BITS
ADDRESS
QS0, QS1, QS2
DS0, DS1, LS
TR
DATA VALID
t_DS
t _DH
ADDRESS VALID
t_AS
t _AH
t _TS
t_W
t_TH
CS
Figure 20a. DAC Input Code Readback
SYMBOL
t_AS
t_RS
t_DV
t_DF
t_AH
t_RH
25°C
MIN (ns)
0
0
150
60
0
0
T_MIN to T_MAX
MIN (ns)
0
0
180
75
0
0
Figure 20b. DAC Input Code Readback Timing
Mode Data Readback
Mode data is read back in a similar fashion. By setting MS, QS0,
QS1, RD and CS low while setting TR and RST high, the mode
select word is presented to the I/O port pins. Figure 21 shows the
timing diagram for a readback of the mode select data register.
Figure 19a. Partially Transparent
SYMBOL
t_DS
t_AS
t_TS
t_W
t_DH
t_AH
t_TH
25°C
MIN (ns)
0
0
0
90
15
15
15
T_MIN to T_MAX
MIN (ns)
0
0
0
110
15
15
15
Figure 19b. Partially Transparent Mode Timing
REV. D
–11–
Figure 21a. Mode Data Readback
SYMBOL
t_AS
t_MS
t_DV
t_DF
t_AH
t_MH
25؇C
MIN (ns)
0
0
150
60
0
0
T_MIN to T_MAX
MIN (ns)
0
0
180
75
0
0
Figure 21b. DAC Mode Readback Timing