AD626_15 Datasheet, PDF (11/13 Pages) Analog Devices – Low Cost, Single-Supply Differential Amplifi er

AD626
necessary to minimize gain error. Also, any mismatch between the
total source resistance at each input will affect gain accuracy and
common-mode rejection (CMR). For example: when operating at
a gain of 10, an 80 ⍀ mismatch in the source resistance between
the inputs will degrade CMR to 68 dB.
The output buffer, A2, operates at a gain of 2 or 20, thus setting
the overall, precalibrated gain of the AD626 (with no external
components) at 10 or 100.The gain is set by the feedback network
around amplifier A2.
The output of amplifier A2 relies on a 10 k⍀ resistor to –V_S for
“pull-down.” For single-supply operation, (–V_S = “GND”), A2
can drive a 10 k⍀ ground referenced load to at least +4.7 V. The
minimum, nominally “zero,” output voltage will be 30 mV. For
dual-supply operation (±5 V), the positive output voltage swing
will be the same as for a single supply. The negative swing will be
to –2.5 V, at G = 100, limited by the ratio:
–V_S
×
R15 + R14
R13 + R14 + R15
The negative range can be extended to –3.3 V (G = 100) and –4 V
(G = 10) by adding an external 10 k⍀ pull-down from the output
to –V_S. This will add 0.5 mA to the AD626’s quiescent current,
bringing the total to 2 mA.
The AD626’s 100 kHz bandwidth at G = 10 and 100 (a 10 MHz
gain bandwidth) is much higher than can be obtained with low
power op amps in discrete differential amplifier circuits. Further-
more, the AD626 is stable driving capacitive loads up to 50 pF
(G10) or 200 pF (G100). Capacitive load drive can be increased
to 200 pF (G10) by connecting a 100 ⍀ resistor in series with the
AD626’s output and the load.
ADJUSTING THE GAIN OF THE AD626
The AD626 is easily configured for gains of 10 or 100. Figure 5
shows that for a gain of 10, Pin 7 is simply left unconnected; simi-
larly, for a gain of 100, Pin 7 is grounded, as shown in Figure 6.
Gains between 10 and 100 are easily set by connecting a variable
resistance between Pin 7 and Analog GND, as shown in Figure 7.
Because the on-chip resistors have an absolute tolerance of ±20%
(although they are ratio matched to within 0.1%), at least a 20%
adjustment range must be provided. The values shown in the
table in Figure 7 provide a good trade-off between gain set range
and resolution, for gains from 11 to 90.
+INPUT
+INPUT
–INPUT
–V_S
0.1␮F
–IN ^200k⍀
1
200k⍀ _+IN
8
ANALOG
2 _GND
1/6
G = 30
G = 100 7
3 –V_S
100k⍀
FILTER
4
AD626
+V_S 6
OUT
G=2
5
+V_S
0.1␮F
OUTPUT
Figure 6. AD626 Configured for a Gain of 100
+INPUT
–INPUT
–IN ^200k⍀
1
200k⍀ _+IN
8
2
ANALOG
GND
1/6
G = 30
R_H
G = 100 7
R_G
–V_S
0.1␮F
CF
FILTER
(OPTIONAL)
3 –V_S
100k⍀
FILTER
4
AD626
+V_S 6
OUT
G=2
5
+V_S
0.1␮F
OUTPUT
CORNER FREQUENCY OF FILTER =
1
2␲CF (100k⍀)
RESISTOR VALUES FOR GAIN ADJUSTMENT
GAIN RANGE
11 – 20
20 – 40
40 – 80
80 – 100
R_G(⍀)
100k
10k
1k
100
R_H(⍀)
4.99k
802
80
2
Figure 7. Recommended Circuit for Gain Adjustment
SINGLE-POLE LOW-PASS FILTERING
A low-pass filter can be easily implemented by using the features
provided by the AD626.
By simply connecting a capacitor between Pin 4 and ground,
a single-pole low-pass filter is created, as shown in Figure 8.
+INPUT
–INPUT
–V_S
0.1␮F
–IN ^200k⍀
1
200k⍀ _+IN
8
2 ^ANALOG
GND
1/6
G = 30
G = 10
7
NOT
CONNECTED
3 –VS
100k⍀
FILTER
4
AD626
+V_S 6
OUT
G=2
5
+V_S
0.1␮F
OUTPUT
–INPUT
CF
–IN ^200k⍀
1
200k⍀ _+IN
8
2
ANALOG
GND
1/6
G = 30
G = 100 7
3 –V_S
100k⍀
FILTER
4
AD626
+V_S 6
OUT
G=2
5
+10V
0.1␮F
OUTPUT
Figure 5. AD626 Configured for a Gain of 10
CORNER FREQUENCY OF FILTER =
1
2␲CF (100k⍀)
Figure 8. A One-Pole Low-Pass Filter Circuit
Which Operates from a Single +10 V Supply
–10–
REV. D