DAC8143EQ Datasheet, PDF(10/12 Page) Analog Devices – 12-Bit Serial Daisy-Chain CMOS D/A Converter

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DAC8143EQ Datasheet, PDF (10/12 Pages) Analog Devices – 12-Bit Serial Daisy-Chain CMOS D/A Converter

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DAC8143

In many applications, the DAC8143âs zero scale error and low

gain error, permit the elimination of external trimming compo-

nents without adverse effects on circuit performance.

For applications requiring a tighter gain error than 0.024% at

25Â°C for the top grade part, or 0.048% for the lower grade part,

the circuit in Figure 17 may be used. Gain error may be trimmed

by adjusting R1.

The DAC register must first be loaded with all 1s. R1 is then

adjusted until VOUT = âVREF (4095/4096). In the case of an

adjustable VREF, R1 and RFEEDBACK may be omitted, with VREF

adjusted to yield the desired full-scale output.

BIPOLAR OPERATION (4-QUADRANT)

Figure 18 details a suggested circuit for bipolar, or offset binary,

operation. Table III shows the digital input-to-analog output

relationship. The circuit uses offset binary coding. Twos comple-

ment code can be converted to offset binary by software inver-

sion of the MSB or by the addition of an external inverter to the

MSB input.

Resistor R3, R4 and R5 must be selected to match within 0.01%

and must all be of the same (preferably metal foil) type to assure

temperature coefficient match. Mismatching between R3 and

R4 causes offset and full-scale error.

Calibration is performed by loading the DAC register with

1000 0000 0000 and adjusting R1 until VOUT = 0 V. R1 and

R2 may be omitted by adjusting the ratio of R3 to R4 to yield

VOUT = 0 V. Full scale can be adjusted by loading the DAC

of VREF or the value of R5 until the desired VOUT is achieved.

Table III. Bipolar (Offset Binary) Code Table

Digital Input

MSB

LSB

1111 1111 1111

1000 0000 0001

Nominal Analog Output

(VOUT as Shown in Figure 18)

+VREF

ï£« 2047 ï£¶

ï£ 2048 ï£¸

+VREF

ï£« 1ï£¶

ï£ 2048 ï£¸

1000 0000 0000 0

0111 1111 1111

0000 0000 0001

0000 0000 0000

âVREF

ï£« 1ï£¶

ï£ 2048 ï£¸

âVREF

ï£« 2047 ï£¶

ï£ 2048 ï£¸

âVREF

ï£« 2048 ï£¶

ï£ 2048 ï£¸

NOTES

1Nominal full scale for the circuits of Figure 18 is given by

ï£« 2047 ï£¶

FS = VREF ï£ 2048 ï£¸ .

2Nominal LSB magnitude for the circuits of Figure 18 is given by

ï£« 1ï£¶

LSB = VREF ï£ 2048 ï£¸ .

DAISY-CHAINING DAC8143s

Many applications use multiple serial input DACs that use

numerous interconnecting lines for address decoding and data

lines. In addition, they use some type of buffering to reduce

loading on the bus. The DAC8143 is ideal for just such an

application. It not only reduces the number of interconnecting

lines, but also reduces bus loading. The DAC8143 can be daisy-

chained with only three lines: one data line, one CLK line and

one load line, see Figure 19.

+5V

50â

VIN

SERIAL

DATA INPUT

100â

12 DGND

VDD

RFB

IOUT1 1

VREF

DAC8143

CONTROL

SRI BITS

CLR SRO

IOUT2 2

AGND 3

10-33pF

1/2 OP200

8-11

4, 5 13 6

COMMON GROUND

20kâ

10kâ

1/2 OP200

FROM

SYSTEM

CONTROL RESET

INPUTS

BUFFERED SERIAL

DATA OUT

Figure 18. Bipolar Operation (4-Quadrant, Offset Binary)

VOUT

â10â

REV. C

▷