ADV7175A_15 Datasheet, PDF (10/50 Pages) Analog Devices – High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder

ADV7175A/ADV7176A
Pin
No.
1, 11, 20,
28, 30
10, 19, 21,
29, 43
15
16
Mnemonic
V_AA
GND
HSYNC
FIELD/VSYNC
17
BLANK
18
ALSB
22
RESET
23
SCLOCK
24
SDATA
25
COMP
26
DAC C
27
DAC D
31
DAC B
32
DAC A
33
V_REF
34
R_SET
35
SCRESET/RTC
36
37
38–42
2–9, 12–14
44
TTXREQ/GND
TTX/V_AA
P0–P15
CLOCK
PIN FUNCTION DESCRIPTIONS
Input/
Output Function
P
Power Supply (3 V to 5 V).
G
Ground Pin.
I/O
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is
logic level “0.” This signal is optional.
I
TTL Address Input. This signal sets up the LSB of the MPU address.
I
The input resets the on chip timing generator and sets the ADV7175A/
ADV7176A into default mode. This is NTSC operation, Timing Slave Mode
0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on.
I
MPU Port Serial Interface Clock Input.
I/O
MPU Port Serial Data Input/Output.
O
Compensation Pin. Connect a 0.1 µF capacitor from COMP to V_AA. For
Optimum Dynamic Performance in Low Power Mode, the value of the
COMP capacitor can be lowered to as low as 2.2 nF.
O
RED/S-Video C/V Analog Output.
O
GREEN/S-Video Y/Y Analog Output.
O
BLUE/Composite/U Analog Output.
O
PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286
mV) for NTSC and 1300 mV for PAL.
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
I
A 150 Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the video signals.
I
This pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a low-
to-high transition on this pin will reset the subcarrier to Field 0. Alternatively
it may be configured as a Real Time Control (RTC) input.
O
Teletext Data Request Signal/Defaults to GND when Teletext not selected
(enables backward compatibility to ADV7175/ADV7176).
I
Teletext Data/Defaults to V_AA when Teletext not selected (enables backward
compatibility to ADV7175/ADV7176).
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.
I
TTL Clock Input. Requires a stable 27 MHz reference Clock for standard
operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be
used for square pixel operation.
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REV. C