AD9843A Datasheet, PDF (10/16 Pages) Analog Devices – Complete 10-Bit 20 MSPS CCD Signal Processor

AD9843A
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register
Address
Data Bits
Name
A0 A1 A2 D0 D1 D2 D3 D4 D5
D6
Operation
0 00
Channel Select Power-Down
CCD/AUX
Modes
Software OB Clamp 0*
Reset On/Off
VGA Gain 1 0 0
LSB
Clamp Level 0 1 0
LSB
Control
1 10
0*
0*
0* CDS Gain Clock Polarity Select for
On/Off SHP/SHD/CLP/DATA
CDS Gain
0 01
LSB
MSB
X
*Internal use only, must be set to zero. **Should be set to one.
SDATA
RNW
TEST
0
A0 A1 A2
0
D0
D1
D2 D3 D4
D5 D6
D7
t_DS
t_DH
SCK
t_LS
SL
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 8. Serial Write Operation
D7 D8
1** 0*
MSB X
0*
0*
X
X
D8 D9 D10
t_LH
D9 D10
0*
0*
MSB X
X
X
Three- X
State
X
X
RNW
TEST
SDATA
1
A0 A1 A2
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t_DS
t_DH
t_DV
SCK
t_LS
t_LH
SL
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK
FALLING EDGES.
Figure 9. Serial Readback Operation
SDATA
RNW A0 A1
00 0 0
11 BITS
OPERATION
10 BITS
AGC GAIN
8 BITS
10 BITS
CLAMP LEVEL CONTROL
0 D0 D1 D2 D3 ^... D10 D0 D1 D2 D3 ... D9 D0 ^... D7 D0 ^... D9
SCK
...
...
...
...
12 34 56 7 8 9
16 17 18 19 20
26 27
34 35
44
SL
...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING
ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Figure 10. Continuous Serial Write Operation to Multiple Registers
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