AD9549ABCPZ Datasheet, PDF (10/76 Pages) Analog Devices – Dual Input Network Clock Generator/Synchronizer

AD9549
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD_I/O 1
DVSS 2
DVDD 3
DVSS 4
DVDD 5
DVSS 6
DVDD 7
DVSS 8
S1 9
S2 10
AVDD 11
REFA_IN 12
REFA_INB 13
AVDD3 14
REFB_IN 15
REFB_INB 16
PIN 1
INDICATOR
AD9549
TOP VIEW
(Not to Scale)
48 DAC_RSET
47 AVDD3
46 AVDD3
45 AVDD
44 AVDD
43 AVSS
42 AVDD
41 FDBK_IN
40 FDBK_INB
39 AVSS
38 OUT_CMOS
37 AVDD3
36 AVDD
35 OUT
34 OUTB
33 AVSS
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL DIE ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Input/
Output Pin Type
1
I
Power
2, 4, 6, 8
I
Power
3, 5, 7
I
Power
9, 10, 54, 55 I/O
3.3 V CMOS
11, 19, 23 to I
26, 29, 30, 36,
42, 44, 45, 53
12
I
Power
Differential
input
13
I
14, 46, 47, 49 I
15
I
Differential
input
Power
Differential
input
16
17, 18
I
Differential
input
Mnemonic
DVDD_I/O
DVSS
DVDD
S1, S2, S3, S4
AVDD
REFA_IN
REFA_INB
AVDD3
REFB_IN
REFB_INB
NC
Description
I/O Digital Supply.
Digital Ground. Connect to ground.
Digital Supply.
Configurable I/O Pins. These pins are configured under program control (see
the Status and Warnings section) and do not have internal pull-up/pull-down
resistors.
Analog Supply. Connect to a nominal 1.8 V supply.
Frequency/Phase Reference A Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
Complementary Frequency/Phase Reference A Input. Complementary signal
to the input provided on Pin 12. If using a single-ended, dc-coupled CMOS
signal into REFA_IN, bypass this pin to ground with a 0.01 μF capacitor.
Analog Supply. Connect to a nominal 3.3 V supply.
Frequency/Phase Reference B Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
Complementary Frequency/Phase Reference B Input. Complementary signal
to the input provided on Pin 15. If using a single-ended, dc-coupled CMOS
signal into REFB_IN, bypass this pin to ground with a 0.01 μF capacitor.
No Connect. These are excess, unused pins that can be left floating.
Rev. D | Page 10 of 76