AD9518-2 Datasheet, PDF (10/64 Pages) Analog Devices – 6-Output Clock Generator with Integrated 2.2 GHz VCO

AD9518-2
SERIAL CONTROL PORT
Table 13.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tH
CS Minimum Pulse Width High, tPWH
PD, SYNC, AND RESET PINS
Table 14.
Parameter
INPUT CHARACTERISTICS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
Data Sheet
Min Typ Max Unit
2.0
V
0.8 V
3
µA
110
µA
2
pF
2.0
V
0.8 V
110
µA
1
µA
2
pF
2.0
10
20
2
V
0.8 V
nA
nA
pF
2.7
V
0.4 V
25 MHz
16
ns
16
ns
2
ns
1.1
ns
8
ns
2
ns
3
ns
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor
Min Typ Max Unit
2.0
V
0.8 V
1
µA
110
µA
2
pF
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up
resistor
50
ns
1.5
High speed High speed clock is CLK input signal
clock cycles
Rev. C | Page 10 of 64