AD8403ARZ10-REEL Datasheet, PDF (10/32 Pages) Analog Devices – 1-/2-/4-Channel Digital Potentiometers

AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Conditions
Min Typ¹ Max
SWITCHING CHARACTERISTICS^{2, 3}
Input Clock Pulse Width
tCH, tCL
Clock level high or low
10
Data Setup Time
tDS
5
Data Hold Time
tDH
5
CLK to SDO Propagation Delay⁴
tPD
RL = 1 kΩ to 5 V, CL ≤ 20 pF
1
25
CS Setup Time
tCSS
10
CS High Pulse Width
tCSW
10
Reset Pulse Width
tRS
50
CLK Fall to CS Rise Hold Time
tCSH
0
CS Rise to Clock Rise Setup
tCS1
10
1 _{Typicals represent average readings at 25°C and VDD = 5 V.}
2 _{Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.}
The remaining resistor terminals are left open circuit.
3 _{See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and}
timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
of 1 V/μs should be maintained.
4 _{Propagation delay depends on the value of VDD, RL, and CL (see the Applications section).}
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAMS
1
SDI
0
1
CLK
0
1
CS
0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
V_OUT ^VDD
0V
Figure 3. Timing Diagram
1
RS
0
V_OUT ^VDD
V_DD/2
t_RS
t_S
±1% ERROR BAND
±1%
Figure 5. Reset Timing Diagram
1
SDI
(DATA IN)
0
SDO ¹
(DATA OUT)
0
1
CLK
0
1
CS
0
V_DD
V_OUT
0V
Ax OR Dx
Ax OR Dx
A'x OR D'x
t_DS
t_DH
A'x OR D'x
t_{PD_MIN}
t_CH
t_{PD_MAX}
t_CS1
t_CSS
t_CL
t_CSH
t_CSW
t_S
±1% ERROR BAND
±1%
Figure 4. Detailed Timing Diagram
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