AD8153 Datasheet, PDF (10/18 Pages) Analog Devices – Single Buffered Switch 3.2 Gbps

AD8153
Preliminary Technical Data
SERIAL CONTROL INTERFACE
REGISTER SET
The AD8153 can be controlled in one of three modes: pin
mode, serial mode, and mixed mode. In pin mode, the AD8153
control is derived from the package pins, whereas in serial
mode a set of internal registers controls the AD8153. There is
also a mixed mode where switching is controlled via external
pins and equalization and pre-emphasis are controlled via the
internal registers. The method for writing data to and reading
data from the AD8153 are described in sections 0 to 0.
The mode is controlled via the MODE pin. To set the part in
pin mode, MODE should be driven low to VEE. When MODE
is driven high to VCC, the part is set to serial or mixed mode.
In pin mode, all controls are derived from the external pins. In
serial mode, each channel’s equalization and pre-emphasis are
solely controlled through the registers as described in Table 8.
Additionally, further functionality is available in serial mode as
each channel’s output can be enabled/disabled with the Output
Enable control bits, which is not possible in pin mode. In order
to change the switching in the AD8153 in serial mode, the mask
bits (register 0x00) must be set to 1 by writing the value 0x1F to
this register as explained in the following sections. Once all the
mask bits are set to 1, switching is controlled via the LB A, LB B,
LB C, BICAST and SEL bits in the register set.
In mixed mode, each channel’s equalization and pre-emphasis
are controlled through the registers as described above. The
switching, however, can be controlled using either the external
pins or the internal register set. The source of the control is
selected using the mask bits (0x00). If a mask bit is set to 0, the
external pin acts as the source for that specific control. If a
mask bit is set to 1, the associated internal register acts as the
source for that specific control. As an example, if one were to
set register 0x00 to the value 0x0C, the SEL and LB C controls
would come from the internal register set (bit 0 of register 0x04
and bit 3 of register 0x03 respectively), and BICAST, LB A and
LB B controls would come from the external pins.
Address
00000000
(0x00)
00000001
(0x01)
00000010
(0x02)
00000011
(0x03)
0000100
(0x04)
Bit 7
Bit 6
Bit 5
Table 8: Register Map
Bit 4
Bit 3
Bit 2
BICAST
MASK
SEL MASK LB_C MASK
OUTPUT
ENABLE A
LB A
EQ A
OUTPUT
ENABLE B
LB B
EQ B
OUTPUT
ENABLE C
LB C
EQ C
Bit 1
LB_B MASK
PE A [1]
PE B [1]
PE C [1]
BICAST
Bit 0
Default
LB_A MASK
00000000
(0x00)
PE A [0]
00010000
(0x10)
PE B [0]
00010000
(0x10)
PE C [0]
00010000
(0x10)
00000000
SEL
(0x00)
GENERAL FUNCTIONALITY
The AD8153 register set is controlled through a two-wire I²C
interface. The AD8153 acts only as an I²C slave device.
Therefore, the I²C bus in the system needs to include an I²C
master in order to configure the AD8153 and other I²C devices
that may be on the bus. Data transfers are controlled through
the use of the two I²C wires: the SCL input clock pin and the
SDA bi-directional data pin. In order to set the AD8153 part in
I²C Mode the MODE input needs to be set high to VCC.
The AD8153 I²C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line only changes value
when the SCL pin is low with two exceptions. In order to
indicate the beginning or continuation of a transfer, the SDA
pin is driven low while the SCL pin is high, and in order to
indicate the end of a transfer, the SDA line is driven high while
the SCL line is high. Therefore, it is important to control the
SCL clock to only toggle when the SDA line is stable unless
indicating a start, repeated start or stop condition.
Rev. PrA | Page 10 of 18