AD8023ARZ Datasheet, PDF (10/11 Pages) Analog Devices – High Current Output, Triple Video Amplifier

AD8023
R_F
+V_S
1.0␮F
0.1␮F
R_G
4
AD8023
1.0␮F
V_IN
11
R_T
0.1␮F
–V_S
15⍀
R_S
V_O
C_L
Figure 31. Circuit for Driving a Capacitive Load
Table II. Recommended Feedback and Series Resistors vs.
Capacitive Load and Gain
C_L – pF
20
50
100
200
300
≥500
R_F – Ohms
2k
2k
2k
3k
3k
3k
R_S – Ohms
G=2
G≥3
0
0
10
10
15
15
10
10
10
10
10
10
V_IN
V_O
Figure 32. Pulse Response Driving a Large Load Capacitor.
C_L = 300 pF, G = +3, R_F = 750 Ω, R_S = 16.9 Ω, R_L = 10 kΩ
Overload Recovery
The three important overload conditions are: input common-
mode voltage overdrive, output voltage overdrive, and input
current overdrive. When configured for a low closed-loop gain,
this amplifier will quickly recover from an input common-mode
voltage overdrive; typically in under 25 ns. When configured for
a higher gain, and overloaded at the output, the recovery time
will also be short. For example, in a gain of +10, with 50%
overdrive, the recovery time of the AD8023 is about 20 ns (see
Figure 31). For higher overdrive, the response is somewhat
slower. For 100% overdrive, (in a gain of +10), the recovery
time is about 80 ns.
V_IN
V_O
Figure 33. 50% Overload Recovery, Gain = +10,
(R_F = 300 Ω, R_L = 1 kΩ, V_S = ±7.5 V)
As noted in the warning under Maximum Power Dissipation, a
high level of input overdrive in a high noninverting gain circuit
can result in a large current flow in the input stage. Though this
current is internally limited to about 30 mA, its effect on the
total power dissipation may be significant.
Disable Mode Operation
Pulling the voltage on any one of the Disable pins about 1.6 V up
from the negative supply will put the corresponding amplifier
into a disabled, powered down, state. In this condition, the
amplifier’s quiescent current drops to about 1.3 mA, its output
becomes a high impedance, and there is a high level of isolation
from input to output. In the case of a gain of two line driver for
example, the impedance at the output node will be about the
same as for a 1.5 kΩ resistor (the feedback plus gain resistors)
in parallel with a 12 pF capacitor.
Leaving the Disable pin disconnected (floating) will leave the
corresponding amplifier operational, in the enabled state. The
input impedance of the disable pin is about 25 kΩ in parallel
with a few picofarads. When driven to 0 V, with the negative
supply at –7.5 V, about 100 µA flows into the disable pin.
When the disable pins are driven by complementary output
CMOS logic, on a single 5 V supply, the disable and enable
times are about 50 ns. When operated on dual supplies, level
shifting will be required from standard logic outputs to the
Disable pins. Figure 33 shows one possible method, which
results in a negligible increase in switching time.
+5
V_I
+7.5V
15k⍀
4k⍀
TO DISABLE PIN
10k⍀
–7.5V
V_I HIGH => AMPLIFIER ENABLED
V_I LOW => AMPLIFIER DISABLED
Figure 34. Level Shifting to Drive Disable Pins on Dual
Supplies
The AD8023’s input stages include protection from the large
differential input voltages that may be applied when disabled.
Internal clamps limit this voltage to about ±3 V. The high input to
output isolation will be maintained for voltages below this limit.
–10–
REV. A