AD8005_15 Datasheet, PDF (10/16 Pages) Analog Devices – 270 MHz, 400A Current Feedback Amplifier

AD8005
Data Sheet
APPLICATIONS
DRIVING CAPACITIVE LOADS
Capacitive loads interact with the output impedance of an op
amp to create an extra delay in the feedback path. This reduces
circuit stability and can cause unwanted ringing and oscillation.
A given value of capacitance causes much less ringing when the
amplifier is used with a higher noise gain.
The capacitive load drive of the AD8005 can be increased by
adding a low valued resistor in series with the capacitive load.
Introducing a series resistor tends to isolate the capacitive load
from the feedback loop, thereby diminishing its influence.
Figure 31 shows the effects of a series resistor on capacitive drive
for varying voltage gains. As the closed-loop gain is increased,
the larger phase margin allows for larger capacitive loads with
less overshoot. Adding a series resistor at lower closed-loop
gains accomplishes the same effect. For large capacitive loads,
the frequency response of the amplifier is dominated by the
roll-off of the series resistor and capacitive load.
R_F
R1
1.5kΩ
V_IN
V_REF
5V
R3
30.1kΩ
R2
1.5kΩ
5V
0.01µF 10µF
AD8005
R4
10kΩ
0.1µF
V_OUT
Figure 32. Bipolar to Unipolar Shift Lever
Figure 32 shows a level shifter circuit that can move a bipolar
signal into a unipolar range. A positive reference voltage, derived
from the +5 V supply, sets a bias level of +1.25 V at the nonin-
verting terminal of the op amp. In ac applications, the accuracy
of this voltage level is not important; however, noise is a serious
consideration. A 0.1 mF capacitor provides useful decoupling of
this noise.
R_G
AD8005
R_S
R_L
1kΩ
C_L
The bias level on the noninverting terminal sets the input common-
mode voltage to +1.25 V. Because the output is always positive,
the op amp can be powered with a single +5 V power supply.
The overall gain function is given by the equation:
Figure 30. Driving Capacitive Loads
80
V_S = ±5V
2V OUTPUT STEP
70 _{WITH 30% OVERSHOOT}
60
R_S = 10Ω
50
40
R_S = 5Ω
30
R_S = 0Ω
20
10
0
1
2
3
4
5
CLOSED-LOOP GAIN (V/V)
Figure 31. Capacitive Load Drive vs. Closed-Loop Gain
SINGLE-SUPPLY LEVEL SHIFTER
In addition to providing buffering, many systems require that an
op amp provide level shifting. A common example is the level
shifting required to move a bipolar signal into the unipolar range
of many modern analog-to-digital converters (ADCs). In general,
single supply ADCs have input ranges that are referenced neither
to ground nor supply. Instead the reference level is some point
in between, usually halfway between ground and supply (+2.5 V
for a single supply 5 V ADC). Because high-speed ADCs typically
have input voltage ranges of 1 V to 2 V, the op amp driving it
must be single supply but not necessarily rail-to-rail.
V_OUT
=
−
R2
R1
^V_IN
+ _{}
R4
R3 + R4
^{1 +}
R2
R1
^V_REF
In the above example, the equation simplifies to
VOUT = −VIN + 2.5 V
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
Many single supply ADCs have differential inputs. In such
cases, the ideal common-mode operating point is usually
halfway between supply and ground. Figure 33 shows how to
convert a single-ended bipolar signal into a differential signal
with a common-mode level of 2.5 V.
+5V
BIPOLAR
SIGNAL
±0.5V
2.49kΩ
0.1µF
2.49kΩ
+5V
R_IN
0.1µF
1kΩ
AD8005
R_F1
2.49kΩ
R_G
619Ω
R_F1
3.09kΩ
+5V
0.1µF
V_OUT
+5V
2.49kΩ
AD8005
2.49kΩ
0.1µF
Figure 33. Single-Ended-to-Differential Converter
Rev. B | Page 10 of 16