AD7741_15 Datasheet, PDF (10/12 Pages) Analog Devices – Single and Multichannel, Synchronous Voltage-to-Frequency Converters

AD7741/AD7742
APPLICATIONS
The basic connection diagram for the part is shown in Figure 9.
In the connection diagram shown, the AD7742 analog inputs
are configured as fully differential, bipolar inputs with a gain of
1. A quartz crystal provides the master clock source for the part.
It may be necessary to connect capacitors (C1 and C2 in the
diagram) on the crystal to ensure that it does not oscillate at over-
tones of its fundamental operating frequency. The values of ca-
pacitors will vary depending on the manufacturer’s specifications.
+5V
DIFF
INPUT 1
V_IN1
V_IN2
DIFF
INPUT 2
V_IN3
V_IN4
A0
CHANNEL
SELECT
A1
V_DD
PD
REFOUT
AD7742
REFIN
f_OUT
GND
UNI/BIP
GAIN
CLKIN
C1
CLKOUT
C2
Figure 9. Basic Connection Diagram
A/D Conversion Techniques Using the AD7741/AD7742
When used as an ADC, VFCs provide certain advantages in-
cluding accuracy, linearity and being inherently monotonic. The
AD7741/AD7742 has a true integrating input which smooths
out noise peaks.
The most popular method of using a VFC in an A/D system is
to count the output pulses of f_OUT for a fixed gate interval (see
Figure 10). This fixed gate interval should be generated by
dividing down the clock input frequency. This ensures that any
errors due to clock jitter or clock frequency drift are eliminated.
The ratio of the f_OUT to the clock frequency is what is important
here, not the absolute value of f_OUT. The frequency division can
be done by a binary counter where f_CLKIN is the CLK input.
Figure 11 shows the waveforms of f_CLKIN, f_OUT and the Gate
signal. A counter counts the rising edges of f_OUT while the Gate
signal is high. Since the gate interval is not synchronized with
f_OUT, there is a possibility of a counting inaccuracy. Depending
on f_OUT, an error of one count may occur.
V_IN
AD7741 ^fOUT
COUNTER
TO ␮P
CLKIN
CLOCK
GENERATOR
FREQUENCY
DIVIDER
GATE
SIGNAL
Figure 10. A/D Conversion Using the AD7741 VFC
f_CLKIN
4096x T_CLOCK
f_OUT
GATE
T_GATE
Figure 11. Waveforms in an A/D Converter Using a VFC
The clock frequency and the gate time determine the resolution
of such an ADC. If 12-bit resolution is required and f_CLKIN is
5 MHz (therefore, f_OUT max is 2.25 MHz), the minimum gate
time required is calculated as follows:
N counts at Full Scale (2.25 MHz) will take
(N/2.25 × 10⁶) seconds = minimum gate time.
N is the total number of codes for a given resolution; 4096 for
12 bits
minimum gate time = (4096/2.25 × 10⁶) sec = 1.820 ms.
Since T_GATE × f_OUT max = number of counts at full scale, a
faster conversion with the same resolution can be performed
with a higher f_OUT max. This high f_OUT max (3 MHz) is a main
feature of the AD7741/AD7742.
If the output frequency is measured by counting pulses gated to
a signal which is derived from the clock, the clock stability is
unimportant and the device simply performs as a voltage-
controlled frequency divider, producing a high resolution ADC.
The inherent monotonicity of the transfer function and wide
range of input clock frequencies allows the conversion time and
resolution to be optimized for specific applications.
There is another parameter is taken into account when choosing
the length of the gate interval. Because the integration period of
the system is equal to the gate interval, any interfering signal can
be rejected by counting for an integer number of periods of the
interfering signal. For example, a gate interval of 100 ms will
give normal-mode rejection of 50 Hz and 60 Hz signals.
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