AD7713_15 Datasheet, PDF (10/28 Pages) Analog Devices – Loop-Powered Signal Conditioning ADC

AD7713
PGA Gain
G2 Gl G0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Gain
1
2
4
8
16
32
64
128
(Default Condition after the Internal
Power-On Reset)
Channel Selection
CH1 CH0 Channel
0 0 AIN1 (Default Condition after the Internal
Power-On Reset)
0 1 AIN2
1 0 AIN3
Word Length
WL Output Word Length
0 16-Bit
(Default Condition after the Internal
Power-On Reset)
1 24-Bit
RTD Excitation Currents
RO
0 Off
(Default Condition after the Internal
Power-On Reset)
1 On
Burn-Out Current
BO
0 Off
(Default Condition after the Internal
Power-On Reset)
1 On
Bipolar/Unipolar Selection (Both Inputs)
B/U
0 Bipolar
(Default Condition after the Internal
Power-On Reset)
1 Unipolar
Filter Selection (FS11 to FS0)
The on-chip digital filter provides a sinc³ (or (sinx/x)³) filter
response. The 12 bits of data programmed into these bits deter-
mine the filter cutoff frequency, the position of the first notch of
the filter, and the data rate for the part. In association with the
gain selection, it also determines the output noise (and therefore
the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by
the relationship: filter first notch frequency = (f_{CLK IN}/512)/code
where code is the decimal equivalent of the code in Bits FS0 to
FS11 and is in the range 19 to 2,000. With the nominal f_{CLK IN}
of 2 MHz, this results in a first notch frequency range from
1.952 Hz to 205.59 kHz. To ensure correct operation of the
AD7713, the value of the code loaded to these bits must be
within this range. Failure to do this will result in unspecified
operation of the device.
Changing the filter notch frequency, as well as the selected gain,
impacts resolution. Tables I and II and Figures 2a and 2b show
the effect of the filter notch frequency and gain on the effective
resolution of the AD7713. The output data rate (or effective
conversion time) for the device is equal to the frequency se-
lected for the first notch of the filter. For example, if the first
notch of the filter is selected at 10 Hz, then a new word is avail-
able at a 10 Hz rate or every 100 ms. If the first notch is at 200 Hz,
a new word is available every 5 ms.
The settling time of the filter to a full-scale step input change is
worst case 4 Ï« 1/(Output Data Rate). This settling time is to 100%
of the final value. For example, with the first filter notch at 100 Hz,
the settling time of the filter to a full-scale step input change is
400 ms max. If the first notch is at 200 Hz, the settling time of
the filter to a full-scale input step is 20 ms max. This settling time
can be reduced to 3 Ï« l/(Output Data Rate) by synchronizing the
step input change to a reset of the digital filter. In other words, if
the step input takes place with SYNC low, the settling time will
be 3 Ï« l/(Output Data Rate). If a change of channels takes place,
the settling time is 3 Ï« l/(Output Data Rate) regardless of the
SYNC input.
The –3 dB frequency is determined by the programmed first
notch frequency according to the relationship:
Filter − 3 dB Frequency = 0.262 × First Notch Frequency
–10–
REV. D