AD744_15 Datasheet, PDF (10/12 Pages) Analog Devices – Precision, 500 ns Settling BiFET Op Amp

AD744
GAIN
ADJUST
100⍀
REF
IN
REF
GND
REF
OUT
V_CC 0.1␮F
BIPOLAR
OFFSET
100⍀ ^ADJUST
10V
19.95k⍀
20k⍀
AD565A
9.96k⍀
20V SPAN
5k⍀
5k⍀
8k⍀
10V SPAN
DAC OUT
0.1␮F
POWER
GND
–V_EE
MSB LSB
C_LEAD
10pF
+15V
1␮F
AD744
1␮F
–15V
Figure 34. ±10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer
HIGH-SPEED OP AMP APPLICATIONS
AND TECHNIQUES
DAC Buffers (I-to-V Converters)
Digital-to-analog converters which use bipolar transistors to
switch currents into (or out of) their outputs can achieve very
fast settling times. The AD565A, for example, is specified to
settle to 12 bits in less than 250 ns, with a current output. How-
ever, in many applications, a voltage output is desirable, and it
would be useful – perhaps essential – that this I-to-V conversion
be accomplished without increasing the settling time or without
degrading the accuracy of the DAC.
Figure 34 is a schematic of an AD565A DAC using an AD744
output buffer. The 10 pF C_LEAD capacitor compensates for the
DAC’s output capacitance, plus the 5.5 pF amplifier input
capacitance.
Figure 35 is an oscilloscope photo of the AD744’s output volt-
age with a +10 V to 0 V step applied; this corresponds to an all
“1s” to all “0s” code change on the DAC. Since the DAC is
A HIGH-SPEED, 3 OP AMP INSTRUMENTATION
AMPLIFIER CIRCUIT
The instrumentation amplifier circuit shown in Figure 36 can
provide a range of gains from unity up to 1000 and higher. The
circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain
of 10; settling time for the entire circuit is less than 2 µs
to within 0.01% for a 10 V step, (G = 10).
While the AD744 is not stable with 100% negative feedback (as
when connected as a standard voltage follower), phase margin
and therefore stability at unity gain may be increased to an accept-
able level by placing the parallel combination of a resistor and a
small lead capacitor between each amplifier’s output and its
inverting input terminal.
The only penalty associated with this method is a small band-
width reduction at low gains. The optimum value for C_LEAD
may be determined from the graph of Figure 41. This technique
can be used in the circuit of Figure 36 to achieve stable opera-
tion at gains from unity to over 1000.
CIRCUIT GAIN = ^20,000 + 1
R_G
AD744
–IN
A1
*1.5pF – 20pF
(TRIM FOR BEST SETTLING TIME)
10k⍀
**10k⍀
7.5pF
**10k⍀
SENSE
R_G
7.5pF
**10k⍀
A3
10k⍀
5pF
AD744
**10k⍀
Figure 35. Upper Trace: AD744 Output Voltage for
a +10 V to 0 V Step, Scale: 5 mV/div.
Lower Trace: Logic Input Signal, Scale: 5 V/div.
connected in the 20 V span mode, 1 LSB is equal to 4.88 mV.
Output settling time for the AD565/AD744 combination is less
than 500 ns to within a 2.44 mV, 1/2 LSB error band.
A2
REFERENCE
+IN
AD744
*VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT
**RATIO MATCHED 1% METAL FILM RESISTORS
+15V
COMM
–15V
+V_S
1␮F
1␮F
–V_S
PIN 7
1␮F
0.1␮F
EACH
AMPLIFIER
1␮F
0.1␮F
PIN 4
FOR OPTIONAL OFFSET ADJUSTMENT:
TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21.
Figure 36. A High Performance, 3 Op Amp
Instrumentation Amplifier Circuit
–10–
REV. C