SSM2602 Datasheet, PDF (1/28 Pages) Analog Devices – Low Power Audio Codec

Preliminary Technical Data
Low Power Audio Codec
SSM2602
FEATURES
GENERAL DESCRIPTION
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 98 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Complete stereo/mono or microphone/line interface
Low power
7 mW stereo playback (1.8 V/1.8 V supplies)
14 mW record and playback (1.8 V/1.8 V supplies)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital core: 1.8 V to 3.6 V
Digital I/O: 1.8 V/3.6 V
256 fS/384 fS or USB master clock rate: 12 MHz, 24 MHz
Audio sample rates: 8 kHz,16 kHz, 32 kHz, 44.1 kHz, 48 kHz,
88.2 kHz, and 96 kHz
28-lead, 5 mm × 5 mm LFCSP (QFN) package
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The SSM2602 is a low power, high quality stereo audio codec
for portable digital audio applications with stereo programmable
gain amplifier (PGA) line and monaural microphone inputs. It
features two 24-bit analog-to-digital converter (ADC) channels
and two 24-bit digital-to-audio (DAC) converter channels.
The SSM2602 can operate as a master or a slave. It offers
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 fS rates, such as 12.288 MHz and
24.576 MHz; and many common audio-sampling rates, such as
96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 16 kHz, and 8 kHz.
The SSM2602 can operate at power supplies as low as 1.8 V for
the analog circuitry and 1.5 V for the digital circuitry. The
maximum voltage supply is 3.6 V for all supplies.
The SSM2602 software-programmable output options provide
the user with many application options, such as speaker driver,
headphone driver, or both. Its volume control functions provide
a large range of gain control of the audio signal.
The SSM2602 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 28-lead, 5 mm × 5 mm
lead frame chip scale package (LFCSP).
FUNCTIONAL BLOCK DIAGRAM
AVDD VMID AGND
DBVDD DGND DCVDD
HPVDD PGND
MICBIAS
–34.5dB~+33dB,
1.5dB STEP
RLINEIN
MICIN
14dB/34dB
LLINEIN
–34.5dB~+33dB,
1.5dB STEP
MUX
MUX
ATTEN
ATTEN
BYPASS/MUTE 3dB STEP
6dB~15dB/MUTE 3dB STEP
ADC
DIGITAL
PROCESSOR
ADC
DAC
DAC
ATTEN
ATTEN
6dB~15dB/MUTE 3dB STEP
BYPASS/MUTE 3dB STEP
SSM2602
–73dB~+6dB,
1dB STEP
RHPOUT
ROUT
LOUT
–73dB~+6dB,
1dB STEP
LHPOUT
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT
XTI
DACDAT ADCDAT BCLK DACLRC ADCLRC MODE CSB SDIN SCLK
Figure 1.
Rev. PrB
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