MAT12 Datasheet, PDF (1/4 Pages) Analog Devices – Low Noise, Matched Dual Monolithic Transistor

Preliminary Technical Data
FEATURES
Low offset voltage (VOS): 50 μV max
Very Low Voltage Noise: 1nV/√Hz max @ 100Hz
High Gain (hFE):
500 min at IC = 1mA
300 min at IC = 1μA
Excellent Log Conformance: rBE = 0.3 Ω
Low Offset Voltage Drift: 0.1 μV/ºC max
High Gain Bandwidth Product: 200MHz
Low Noise, Matched
Dual Monolithic Transistor
MAT12
PIN CONFIGURATION
Note: Substrate is connected to case on TO-78 package. Substrate is
normally connected to the most negative circuit potential, but can
be floated
GENERAL DESCRIPTION
The design of the MAT12 series of NPN dual monolithic transistors is optimized for very low noise, low drift and
low r_BE. Exceptional characteristics of the MAT12 include offset voltage of 50 µV max and high current gain (hFE)
which is maintained over a wide range of collector current. Device performance is specified over the full
temperature range as well as at 25°C.
Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device
characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the
parasitic isolation junction created by the protection diodes. This results in complete isolation between the
transistors.
The MAT12 is ideal for applications where low noise is a priority. The MAT12 can be used as an input
stage to make an amplifier with noise voltage of less than 1.0 nV/√Hz at 100 Hz. Other applications, such as
log/antilog circuits, may use the excellent logging conformity of the MAT12. Typical bulk resistance is only 0.3
Ω to 0.4 Ω. The MAT12 electrical characteristics approach those of an ideal transistor when operated over a
collector current range of 1µA to 10 mA.
Rev. PrA
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