HMC794LP3E Datasheet, PDF (1/10 Pages) Hittite Microwave Corporation – 2 GHz LOW NOISE PROGRAMMABLE DIVIDER (N = 1 to 4)

v01.0612
Typical Applications
The HMC794LP3E is ideal for:
• LO Generation with Low Noise Floor
• Clock Generators
• Mixer LO Drive
• Military Applications
• Test Equipment
• Sensors
Functional Diagram
HMC794LP3E
2 GHz LOW NOISE PROGRAMMABLE
DIVIDER (N = 1 to 4)
Features
Low Noise Floor: -163 dBc/Hz at 10 MHz offset
and -160 dBc/Hz at 100 kHz offset
Programmable Frequency Divider, N = 1, 2, 3 or 4
200 MHz to 2 GHz Input Frequency Range
50% Duty Cycle Outputs
Up to +10 dBm Output Power
Sleep Mode: Consumes <1 µA
16 Lead 3X3 mm SMT Package: 9mm²
General Description
The HMC794LP3E is a SiGe BiCMOS low noise
programmable frequency divider in a 3x3mm lead-
less surface mount package. The circuit can be
programmed to divide from N = 1 to N = 4 in the
200 MHz to 2 GHz input frequency range. The high
level output power (up to 10 dBm) with a very low
SSB phase noise and 50% duty cycle makes this
device ideal for low noise clock generation, LO
generation and LO drive applications. Configurable
bias controls allow power minimization of up to 20%.
Electrical Specifications, T_A = +25° C, Vcc = +5V, Zo = 50Ω, Bias1 = GND
Parameter
RF Input Characteristics
Max RF Input Frequency
Min RF Input Frequency
RF Input Power
Divider Output Characteristics
Differential Output Power
SSB Phase Noise @ 10 MHz Offset
SSB Phase Noise @ 100 kHz Offset
SSB Phase Noise @ 10 kHz Offset
Duty Cycle for Differential Mode
Logic Inputs
VIH Input High Voltage
VIL Input Low Voltage
Conditions
Note: best SSB Phase Noise for Pin > 5 dBm
Programmable in 2 steps
(see the Pout plots for each division ratio)
+5 dBm Input Power, 2 GHz Input
+5 dBm Input Power
Min.
Typ.
200
-2
3
-3
10
-163
-160
-153
50 ±3
3
0
Max.
2
10
12
5
0.4
Units
GHz
MHz
dBm
dBm
dBc/Hz
dBc/Hz
dBc/Hz
%
V
V
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