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CN-0259 Datasheet, PDF (1/5 Pages) Analog Devices – High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter and 184.32 MSPS Sampling Rate
Circuit Note
CN-0259
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0259.
Devices Connected/Referenced
AD6657A Quad IF Receiver, 200 MSPS Sampling Rate
ADL5565
6.0 GHz Ultrahigh Dynamic Range
Differential Amplifier
High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter
and 184.32 MSPS Sampling Rate
EVALUATION AND DESIGN SUPPORT
Design and Integration Files
Schematics, Layout Files, Bill of Materials
CIRCUIT FUNCTION AND BENEFITS
The circuit, shown in Figure 1, is a 65 MHz bandwidth receiver
front end based on the ADL5565 ultrahigh dynamic range
differential amplifier driver and the 11-bit, 200 MSPS
AD6657A quad IF receiver.
The fourth-order Butterworth antialiasing filter is optimized based
on the performance and interface requirements of the amplifier
and IF receiver. The total insertion loss due the filter network
and other resistive components is only 2.0 dB. The overall circuit
has a bandwidth of 65 MHz, with the low-pass filter having a
1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz.
The pass-band flatness is 1 dB.
The circuit is optimized to process a 65 MHz bandwidth IF signal
centered at 140 MHz with a sampling rate of 184.32 MSPS. The
SNR and SFDR measured with a 140 MHz analog input across
the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively.
0.1dB LOSS
6dB GAIN
2.0dB LOSS
1.875dB LOSS
0.125dB LOSS
ANALOG
INPUT
+4.9dBm
AT 10MHz
INPUT
Z = 50Ω
XFMR
1:1 Z
ECT 1-1-13M
OVERALL GAIN = 3.9dB
0.1µF
40Ω
ZI = 200Ω
0.1µF
40Ω
+3.3V
RA
20Ω
0.1µF
VIP2
VIP1
VIN1
VIN2
5Ω
ADL5565
G = 6dB
5Ω
RA 0.1µF
20Ω
249Ω
FILTER
72nH
110nH
7.5pF
0.1µF
72nH
110nH
50Ω
209Ω
+1.8V
RKB
15Ω
110Ω
RTADC
1.5pF
110Ω
RTADC
RADC
2.4kΩ
VCM
AD6657A
11-BIT
200MSPS
IF RECEIVER
2.2pF
INTERNAL
INPUT Z
RKB
15Ω
FS 1.75V p-p DIFF
Figure 1. Single Channel of Quad IF Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown)
Gains, Losses, and Signal Levels Measured Values at 10 MHz
Rev. B
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