AN-502 Datasheet, PDF (1/12 Pages) Analog Devices – Designing a Superheterodyne Receiver Using an IF Sampling Diversity Chipset

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AN-502
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Designing a Superheterodyne Receiver Using an IF Sampling Diversity Chipset
by Brad Brannon
Abstract: The paper introduces a chipset to simplify re-
ceiver design and puts forth a design example based on
GSM but can be extended to many open or closed air
interface. Advances in analog converter technology
now allow IF sampling which can greatly simplify re-
ceiver design. Advances in digital integrated circuits
also advance the state of the art in terms of digital tun-
ing and filtering. Together these two chips can replace
many of the cumbersome stages of a traditional analog
receiver with predictable and reliable performance.
The superheterodyne receiver is still a workhorse in re-
ceiver technology. It has served its duty faithfully for
many years now. However new technologies in receiver
component designs are offering to extend the possibili-
ties into the digital age.
A typical receiver design may consist of two or three
down conversions to provide the sensitivity and selec-
tivity required of the individual receiver. With each
down conversion, a local oscillator, mixer and filter are
required. Each additional stage adds complexity, cost
and difficulty of manufacture.
FILTER
&
LNA
FILTER
&
LNA
FILTER
&
LNA
DETECTOR
LO
LO
LO
PROCESS
Figure 1. Typical Receiver Block Diagram
As shown above in the block diagram, receiver technol-
ogy can be “straight forward”, however, implementa-
tion and manufacture can be another story.
There are several key issues that must be addressed. Of
course, the issues of noise and intercept point are al-
ways of concern when it comes to receiver design.
However, in moderate and high volume applications,
questions about assembly and test begin to arise. It is
one thing to build one in the lab, but it is a completely
different story to build many in production. With three
local oscillators, mixers and IF strips, alignment can be
a real issue, even with automated tools. To keep
manufacturing cost low, several of these analog stages
must be eliminated, but how can this be done without
sacrificing performance? Perhaps the real question is
can performance be enhanced. One solution is to digi-
tize the analog signals and do the processing in a DSP.
Once in the digital domain, many creative and propri-
etary processes can take place to enhance and add
value, while eliminating many of the manufacturing
problems (alignment and component yield) that often
increase the cost of manufacturing and reduce margins.
Already, it is common practice to use an analog-to-
digital converter to form the detector and a DSP (digital
signal processor) to process the data. However, this
does not reduce the cost or complexity of the design (to
digitize the baseband), it simply adds flexibility. What is
needed is an analog to digital converter that can digitize
closer to the antenna. Sampling at the antenna is not
realistic since some amount of band select and filtering
must occur prior to the ADC to minimize adjacent chan-
nel issues. However, sampling at the first IF is practical.
FILTER &
LNA
FILTER &
LNA
ADC
DSP
LO
Figure 2. Digital Receiver Block Diagram
IF SAMPLING
Recent advances in converter technology have allowed
data converters to faithfully sample analog signals as
high as several hundred MHz. Sample rates need only
be as high as twice the signal bandwidth to keep the
Nyquist principle. Since most air interface standards
are less than a few MHz wide, sample rates in the tens of
MHz are required, eliminating the need for extremely
fast sample rates in radio design. Thus allowing for low
cost digitizers.
One such analog to digital converter (ADC) that per-
forms this function is the AD6600. The AD6600 can
digitize up to 20 MSPS and sample analog signals up to
250 MHz with 60 dB spurious free dynamic range. In ad-
dition to high performance data conversion, this ADC
also includes gain control and dual inputs to facilitate
diversity applications.