AN-1039 Datasheet, PDF (1/8 Pages) Analog Devices – Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity

AN-1039
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: [phone] • Fax: [phone] • www.analog.com
Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity
by Eamon Nash
INTRODUCTION
The in-phase and quadrature modulator (IQ modulator) is a
key component in modern wireless transmitters. It provides a
convenient method for modulating data bits or symbols onto
an RF carrier. IQ upconversion has become the architecture
of choice for implementing transmitter signal chains for end
applications such as cellular, WiMAX, and wireless point-to-
point. IQ modulators, however, can degrade signal fidelity in
ways that are somewhat unique. These effects can degrade the
quality of the transmitted signal during the modulation process,
resulting in degraded error vector magnitude (EVM) at the
receiver, which in turn degrades bit error rate (BER). Fortu-
nately, algorithms exist that can correct these imperfections.
This application note describes a typical zero-IF or direct-
conversion transmitter and provides a brief introduction to
digital modulation. Other items discussed are: the imper-
fections introduced by the modulator are examined with
particular focus on the effect of temperature and frequency
changes, in-factory and in-field algorithms that can reduce the
effect of these modulator imperfections is also discussed, and
particular focus is placed on the efficacy of in-factory set-and-
forget algorithms.
A TYPICAL WIRELESS TRANSMITTER
Figure 1 shows a block diagram of a direct-conversion wireless
transmitter that uses an IQ modulator to modulate a bit stream
onto a carrier. A single bit stream is split into two parallel bit
streams at half the original data rate. To limit the spectral band-
width of the final carrier, the two bit streams are low-pass filtered
in the digital domain. To do this, the original bit-streams must
be digitally oversampled by the digital signal processor or field
programmable gate array (FPGA). So, instead of two bit streams,
there are now two streams of digital words. The chosen resolu-
tion of these words depends upon multiple factors such as the
required signal-to-noise ratio of the link and the chosen mod-
ulation scheme (QPSK in this case). Word widths between 12
and 16 bits are commonly chosen.
FPGA OR DSP
800
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0
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1.0
1.5
2.0
TIME (msec)
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1.5
2.0
TIME (msec)
OVERSAMPLE
LOW-PASS
FILTER
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0
–200
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AD9788
AUX
DAC1
GAIN
DAC 1
DIGITAL
FILTER
PHASE
ADJUST
16-BIT
I DAC
50Ω
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0
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1.329
1.829
TIME (msec)
2.329
OVERSAMPLE
LOW-PASS
FILTER
AUX
DAC2
GAIN
DAC 2
DIGITAL
FILTER
PHASE
ADJUST
16-BIT
Q DAC
50Ω
Q
I
LOW-
PASS
FILTER
100Ω
ADL5375
0°
90°
LOW-
PASS
FILTER
100Ω
ADL5320 ^HPA
AD8363
50dB RMS
DETECTOR
SPECTRUM
ANALYZER
DIGITAL
DEMOD
AD9230
AD8352
Figure 1. A Zero IF Direct-Conversion Transmitter with Optional Loop-Back Receiver
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